Abstract: According to one embodiment, a semiconductor memory device includes a substrate that includes a first region and a second region; a stacked body that is disposed on the first region of the substrate and includes a plurality of first metal layers and a plurality of voids each of which is disposed between the plurality of first metal layers; a columnar portion that penetrates the stacked body, extends in a direction of stacking in the stacking body; a transistor that is disposed on the second region; and the interconnect portion that is disposed on the transistor and includes the plurality of first metal layers and a plurality of second metal layers each of which is disposed between the plurality of first metal layers. The transistor is electrically connected to the channel body or the first metal layer of the stacked body through a interconnect portion.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer, which is provided between the semiconductor layer and the control gate electrode, and has organic molecules including a molecular structure described by a molecular formula (1).

Abstract: According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each other; a second layer provided between the first layer and the stacked body; an intermediate layer provided between the first layer and the second layer; a semiconductor body provided in the stacked body, the second layer, the intermediate layer and the first layer, the semiconductor body extending in a stacking direction of the stacked body; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The semiconductor body includes a side surface connected with the intermediate layer in the vicinity of a boundary between the first layer and the second layer. At least one of the first layer and the second layer has conductivity and is connected with the intermediate layer.

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers each provided between adjacent ones of the electrode layers; and a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; a charge storage film provided between the channel body and the electrode layer; and a gap provided between the charge storage film and the electrode layer.

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells stacked on the substrate; an inter-layer insulating layer provided on the memory cell array; and a first control circuit. The first control circuit includes a first transistor and first semiconductor layer, a number of a grain boundary of the first semiconductor layer is not less than a number of a grain boundary of the substrate, and the first control circuit is provided on the inter-layer insulating layer and electrically connected to the memory cells.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film.

Abstract: According to one embodiment, a waveguide includes: a substrate and a member. The member covers at least a part of the substrate and has a difference in the refractive index from the substrate not less than 2. A plurality of concave parts are provided on the substrate. The concave parts are arrayed on an upper face of the substrate. At least a part of a side face of each of the concave parts includes an arc. An inner diameter of each of the concave parts is not more than 50 nm. Intervals of the neighboring concave parts are not more than the inner diameter. The member fills the concave part.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer, a control gate electrode, and an organic molecular layer provided between the semiconductor layer and the control gate electrode and having an organic molecule including a porphyrin structure.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film.

Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.

Abstract: A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.