Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.

Abstract: A magnetic storage element according to an embodiment includes: a magnetic nanowire having a cross-sectional area varying in a first direction, the magnetic nanowire having at least two positions where the cross-sectional area is minimal; first and second electrode groups having the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a first region where the first electrodes overlap the second electrodes with the magnetic nanowire interposed in between and a second region where neither the first electrodes nor the second electrodes exist with the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a third region where the first electrodes exist and the second electrodes do not exist with the magnetic nanowire interposed in between and a fourth region where the first electrodes do not exist and the second electrodes exist with the magnetic nanowire interposed in between.

Abstract: A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2<DEOT<Dk??(1) Dsio2 denotes a thickness of the dielectric when the dielectric is composed of silicon oxide with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers. Dk denotes such an equivalent oxide thickness of a first dielectric that provides the resistance value Rsio2. The resistance value Rsio2 being defined as a resistance value of the first semiconductor layer for each of the first conductive layers when the dielectric is composed of silicon oxide and has a film thickness of Dsio2.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a second insulating layer, a select gate, a memory hole, a memory film, a channel body, a first semiconductor layer, and a second semiconductor layer. The select gate is provided on the second insulating layer. The memory film is provided on an inner wall of the memory hole. The channel body is provided inside the memory film. The first semiconductor layer is provided on an upper surface of the channel body. The second semiconductor layer is provided on the first semiconductor layer. The first semiconductor layer contains silicon germanium. The second semiconductor layer contains silicon germanium doped with a first impurity. A boundary between the first semiconductor layer and the second semiconductor layer is provided above a position of an upper end of the select gate.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of electrically rewritable memory transistors arranged therein; and a control unit configured to govern control that repeats a voltage application operation and a step-up operation, the voltage application operation applying an applied voltage to a selected memory transistor to change a threshold voltage at which the selected memory transistor is conductive, and the step-up operation, in the case where a threshold voltage of the selected memory transistor has not changed to a desired value, raising the applied voltage by an amount of a certain step-up value. The control unit is configured to control the step-up operation to monotonically decrease the step-up value as the number of times of the voltage application operations increases.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, an insulating film, and a charge storage film. The stacked body includes a plurality of electrode films stacked with an inter-layer insulating film provided between the electrode films. The semiconductor pillar pierces the stacked body. The insulating film is provided between the semiconductor pillar and the electrode films on an outer side of the semiconductor pillar with a gap interposed. The charge storage film is provided between the insulating film and the electrode films. The semiconductor pillar includes germanium. An upper end portion of the semiconductor pillar is supported by an interconnect provided above the stacked body.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a select gate electrode, a semiconductor pillar, a memory layer, and a select gate insulating film. The stacked structure includes a plurality of electrode films stacked in a first direction and an interelectrode insulating film provided between the electrode films. The select gate electrode is stacked with the stacked structure along the first direction and includes a plurality of select gate conductive films stacked in the first direction and an inter-select gate conductive film insulating film provided between the select gate conductive films. The semiconductor pillar pierces the stacked structure and the select gate electrode in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The select gate insulating film is provided between the select gate conductive films and the semiconductor pillar.

Abstract: A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

Abstract: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

Abstract: In this embodiment, a mask material is formed above a film to be processed, and a plurality of sacrifice films are formed above the mask material, each of the sacrifice films having a columnar shape. Then, a sidewall film is formed on a sidewall of the sacrifice films, and then the sacrifice films are removed. Thereafter, the sidewall films are caused to flow. In addition, a plurality of holes are formed in the mask material using the sidewall film as a mask. Then, isotropic etching is performed for the mask material to etch back the sidewall of the mask material with respect to a sidewall of the sidewall film by a first distance. Thereafter, a deposition layer is deposited inside the plurality of holes to close an opening of the plurality of holes with the deposition layer. Anisotropic etching is conducted to remove the deposition layer in the opening.

Abstract: A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.

Abstract: According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

Abstract: A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other along a direction in which the magnetic nanowire extends, the second control electrode group including a plurality of second control electrodes arranged to be spaced apart from each other to correspond to the plurality of first control electrodes along the direction in which the magnetic nanowire extends, and the second control electrodes corresponding to the first control electrodes being shifted in the direction in which the magnetic nanowire extends; a first driving unit for driving the first control electrode group; and a second driving unit for driving the second control electrode group.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film.

Abstract: A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.