Patents by Inventor Yoshiaki Saito
Yoshiaki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150357016Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.Type: ApplicationFiled: August 21, 2015Publication date: December 10, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Yoshiaki SAITO, Tetsufumi TANAMOTO
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Publication number: 20150311305Abstract: An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mizue ISHIKAWA, Tomoaki INOKUCHI, Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Yoshiaki SAITO
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Publication number: 20150269513Abstract: A work schedule of a user who uses an automatic analyzer is input from an input unit 120. A planning section 112 schedules in advance task events required for using the automatic analyzer. A schedule preparing section 113 prepares, from the work schedule input from the input unit and the task events scheduled by the planning section, a time-series task schedule as a list of tasks to be performed by the user within a period of time allocated to him or her. A display unit 130 displays the task schedule prepared by the schedule preparing section. The foregoing arrangements enable specific tasks to be performed by the user within the period of time allocated to him or her to be predicted in advance, the tasks to be efficiently scheduled according to the work schedule of the user, and each and every task to be performed without any omission.Type: ApplicationFiled: October 22, 2013Publication date: September 24, 2015Inventors: Yasuo Kaneko, Yoshiaki Saito
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Patent number: 9112139Abstract: A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.Type: GrantFiled: June 18, 2012Date of Patent: August 18, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki Inokuchi, Takao Marukame, Tetsufumi Tanamoto, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito
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Patent number: 9112131Abstract: A spin MOSFET includes a first ferromagnetic layer having a fixed magnetization direction, a first tunnel barrier, a second ferromagnetic layer having a variable magnetization direction, and a nonmagnetic semiconductor layer provided in that order on a substrate. The nonmagnetic semiconductor layer has lower and upper faces and a side faces serving as a channel. A third ferromagnetic layer having a fixed magnetization direction is provided on the upper face of the nonmagnetic semiconductor layer, wherein the magnetization direction of each of the first to third ferromagnetic layers is in parallel or antiparallel to a direction from the third ferromagnetic layer to the first ferromagnetic layer. A nonmagnetic layer is provided on the third ferromagnetic layer, and a gate insulating film and gate electrode are provided in that order on the side face of the nonmagnetic semiconductor layer.Type: GrantFiled: December 13, 2013Date of Patent: August 18, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
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Publication number: 20150204895Abstract: An automatic analyzer is capable of ensuring sufficient nozzle cleaning and suppressing of deterioration in the accuracy of analysis. When it is judged that there remains no analysis item of the sample, a judgment is made on whether the sample dispensation quantity of the n-th sample dispensation is less than a dispensation quantity threshold value or not, and if less, a cleaning pattern is selected by making a judgment on whether or not all the sample dispensation quantities of the first through (n?1)-th sample dispensations are less than the dispensation quantity threshold value. If the sample dispensation quantity of the n-th sample dispensation is the dispensation quantity threshold value or more, another cleaning pattern selected by making the judgment on whether or not all the sample dispensation quantities of the first through (n?1)-th sample dispensations are less than the dispensation quantity threshold value.Type: ApplicationFiled: July 25, 2013Publication date: July 23, 2015Inventors: Akihiro Yasui, Hitoshi Tokieda, Toshihide Orihashi, Yoshiaki Saito, Naoto Suzuki
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Patent number: 9085874Abstract: A working vehicle has improved operability and working efficiency during loading. A loading operation detector detects the start of a loading operation based on at least two of the following: whether a boom lever has been operated in its raise direction; whether a boom is in an attitude set in advance; whether the boom angle is less than an upper limit; whether a speed ratio when a brake is OFF is greater than or equal to a predetermined value; whether a predetermined speed stage is set; whether the traveling range has been changed from reverse to forward; and whether the angular velocity of the boom is greater than or equal to a predetermined value. By increasing the discharge amount of a loader pump, and/or by supplying hydraulic fluid to a boom cylinder from a switch pump, a hydraulic fluid amount increase controller supplies more hydraulic fluid to the boom.Type: GrantFiled: July 22, 2008Date of Patent: July 21, 2015Assignee: KOMATSU LTD.Inventor: Yoshiaki Saito
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Publication number: 20150153370Abstract: The present invention provides an automated analyzer that can effectively reduce contamination of a diluted low-concentration specimen resulting from a high-concentration specimen not being diluted. The automated analyzer includes a specimen nozzle that performs both the function of pipetting a specimen from a specimen container accommodating the specimen and the function of pipetting a specimen diluted by the analyzer, and means for washing the specimen nozzle with a predetermined detergent. When a pipetting process of a high-concentration specimen not being diluted and a pipetting process of a low-concentration specimen diluted by the analyzer are consecutively performed for the same specimen by the specimen nozzle, between the pipetting process of a high-concentration specimen and the pipetting process of a low-concentration specimen, the analyzer performs a washing processing in which the specimen nozzle is washed with the predetermined detergent.Type: ApplicationFiled: July 8, 2013Publication date: June 4, 2015Inventors: Yoshiaki Saito, Yoichi Aruga, Toshihide Orihashi
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Patent number: 8981436Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.Type: GrantFiled: September 30, 2013Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto
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Patent number: 8958239Abstract: One embodiment provides a magnetic memory element, including: a first ferromagnetic layer whose magnetization is variable; a second ferromagnetic layer which has a first band split into a valence band and a conduction band and a second band being continuous at least from the valence band to the conduction band; and a nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer.Type: GrantFiled: June 26, 2012Date of Patent: February 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito
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Publication number: 20140363896Abstract: When the type is to be changed from serum (preceding sample) to urine (current sample), “serum” is set to a preceding type and “urine” is set to a measurement type at number 1 in a condition number. At condition number 1, the wash type is pattern 1, with washing performed once with detergent 1. Where the preceding sample is serum and the current sample is CSF, the condition number is 2 and the wash type is pattern 2, with washing performed twice using detergent 1 and once with detergent 2. Where the preceding sample is urine and the current sample is CSF, the condition number is 3 and the wash type is pattern 3, with washing performed once with detergent 1, once with detergent 2, and once with water. In the case of pattern 4, washing is performed three times with detergent 1.Type: ApplicationFiled: December 14, 2012Publication date: December 11, 2014Inventors: Naoto Suzuki, Yoshiaki Saito, Yoichi Aruga, Toshihide Orihashi, Kazuhiro Nakamura
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Publication number: 20140301136Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.Type: ApplicationFiled: March 11, 2014Publication date: October 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Akira TAKASHIMA, Yoshiaki SAITO
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Publication number: 20140291744Abstract: A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more.Type: ApplicationFiled: June 10, 2014Publication date: October 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki SAITO, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa
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Patent number: 8847288Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.Type: GrantFiled: January 25, 2013Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 8779496Abstract: A spin FET includes a first ferromagnetic film disposed on a first source/drain area, a direction of magnetization thereof being fixed in an upward direction or a downward direction perpendicular to a film surface, a second ferromagnetic film disposed on a second source/drain area, a direction of magnetization thereof being changed in the upward direction or the downward direction, an anti-ferromagnetic ferroelectric film disposed on the second ferromagnetic film, and a tunnel barrier film disposed at least between the first source/drain area and the first ferromagnetic film or between the second source/drain and the second ferromagnetic film. Resistance of the anti-ferromagnetic ferroelectric film is larger than ON resistance when the first and second source/drain areas conduct electricity through the channel area.Type: GrantFiled: February 11, 2008Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
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Publication number: 20140170023Abstract: In determining whether a rack inputted to the automatic analyzer by the user is to be transferred to an analysis section or not, samples existing in a route from a buffer to a sample dispensing position in the analysis section are identified, and the number of items in which suction by a nozzle has not been completed in analysis items requested for the samples is managed. When the number of items is reduced to be smaller than a given number, the conveyance of a next rack from the buffer to the analysis section is controlled, thereby limiting the number of analysis items requested for samples in a waiting state for analysis in the analysis section constantly to be smaller than a fixed number. As a result, a period of time until a measurement result of emergency samples is outputted can be reduced even when emergency samples are newly inputted.Type: ApplicationFiled: June 29, 2012Publication date: June 19, 2014Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Yoshiaki Saito, Kazuhiro Nakamura, Naoto Suzuki, Toshihide Orihashi
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Patent number: 8725358Abstract: An object of the present invention is to prevent an unnecessary large amount of hydraulic oil from being supplied to a cylinder when a working vehicle capable of performing both a loading operation and a digging operation is performing the digging operation. When one or a plurality of first digging operation conditions are satisfied and when a second operation condition that it is not detected that the loading operation is being performed is also satisfied, a control unit executes fluid amount reduction control of reducing the amount of hydraulic oil supplied from a first pump to a cylinder that actuates a work equipment.Type: GrantFiled: March 11, 2009Date of Patent: May 13, 2014Assignee: Komatsu LtdInventors: Takahide Takiguchi, Satoshi Matsumoto, Yoshiaki Saito
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Publication number: 20140117427Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.Type: ApplicationFiled: September 30, 2013Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki SAITO, Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto
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Publication number: 20140097474Abstract: A spin MOSFET includes a first ferromagnetic layer having a fixed magnetization direction, a first tunnel barrier, a second ferromagnetic layer having a variable magnetization direction, and a nonmagnetic semiconductor layer provided in that order on a substrate. The nonmagnetic semiconductor layer has lower and upper faces and a side faces serving as a channel. A third ferromagnetic layer having a fixed magnetization direction is provided on the upper face of the nonmagnetic semiconductor layer, wherein the magnetization direction of each of the first to third ferromagnetic layers is in parallel or antiparallel to a direction from the third ferromagnetic layer to the first ferromagnetic layer. A nonmagnetic layer is provided on the third ferromagnetic layer, and a gate insulating film and gate electrode are provided in that order on the side face of the nonmagnetic semiconductor layer.Type: ApplicationFiled: December 13, 2013Publication date: April 10, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
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Patent number: 8681033Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.Type: GrantFiled: June 27, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takao Marukame, Tetsufumi Tanamoto, Atsuhiro Kinoshita, Tomoaki Inokuchi, Masamichi Suzuki, Yoshiaki Saito