Abstract: A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.

Abstract: Problems of work efficiency reduction by tire slip; durability reduction by tire damage; and large tire-changing costs for users are solved by preventing repeated tire slip occurrence in situations where tire slip likely occurs such as during excavation. A working vehicle of this invention has a work equipment, and an engine power is transmitted as driving force to the tires via a driving force transmission path. Driving force variation means for freely varying the driving force transmitted to the tires is provided in the transmission path of the working vehicle. Tire slip detection means detects tire slip occurrence. When the tire slip detection means detects tire slip, driving force measurement means measures the driving force at the time of tire slip detection. Driving force control means controls the driving force variation means such that the driving force becomes smaller than that at the time of tire slip detection.

Abstract: A spin transistor includes a source electrode, a drain electrode, and a gate electrode on a semiconductor substrate. At least one of the source electrode and the drain electrode includes a semiconductor region and a magnetic layer. The semiconductor region is formed in the semiconductor substrate. The magnetic layer is formed on the semiconductor region, and contains a crystalline Heusler alloy containing at least one of cobalt (Co) and iron (Fe). The semiconductor region and the magnetic layer contain the same impurity element.

Abstract: A control device for a work machine on a construction vehicle is provided so that a bucket cylinder is stopped at a target position, with high accuracy achieved in a bucket cylinder length, and with chock held down to a low level. A bucket cylinder length detection section references a cylinder length detection table on the basis of a boom angle and a bell crank angle, thereby detecting a bucket cylinder length. A bucket attitude control section controls the bucket cylinder length so that a target position will be reached. Feedback control is performed until a set value which is set short of a target value is reached. After the bucket cylinder length reaches the set value, open loop control is performed until the target value is reached.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

Abstract: A working vehicle of the present invention achieves more stabilized constant speed traveling. A vehicle speed control section 20A of a controller 2 calculates a target drive force required for constant speed traveling on the basis of a preset standard traveling resistance (S1). And, on the basis of an output rotational speed (S2) and the target drive force (S1) of a torque converter 14, the vehicle speed control section 20A determines a target input rotational speed (S3) to be inputted to the torque converter 14, and sets a clutch pressure (S5) so as to eliminate a difference between the target input rotational speed and an actual input rotational speed (S4). A standard traveling resistance correction section 20B corrects a standard traveling resistance according to state of a road surface, long term change of components, and so on. Due to this, it is possible to perform stabilized constant speed traveling.

Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.

Abstract: A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.

Abstract: A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode.

Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.

Abstract: A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.

Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

Abstract: A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.

Abstract: A spin memory includes a magneto-resistance element having a first ferromagnetic layer in which a magnetization direction is pinned, a second ferromagnetic layer in which a magnetization direction changes, and a first nonmagnetic layer between the first and second ferromagnetic layers, a lower electrode and an upper electrode extending in a direction between 45 degrees and 90 degrees relative to an axis of hard magnetization of the second ferromagnetic layer, and sandwiching the magneto-resistance element at one end in a longitudinal direction, a switching element connected to another end in a longitudinal direction of the lower electrode, and a bit line connected to another end in a longitudinal direction of the upper electrode, wherein writing is carried out by supplying spin-polarized electrons to the second ferromagnetic layer and applying a magnetic field from the lower electrode and the upper electrode to the second ferromagnetic layer.

Abstract: A specimen rack and a specimen carrier system includes a luminous body disposed on a vicinity of a specimen container loading slot to notify, to an operator, information concerning an analyzing situation and condition of the specimen contained in the specimen container held by the specimen rack.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.

Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

Abstract: Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.