Patents by Inventor Yoshiaki Yamada

Yoshiaki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020062683
    Abstract: In a chromatograph comprising a pump, a sample injecting unit, a column, a photo-diode array detector and a data processing unit having a spectrum library of registered spectrums of known components, a spectrum selected in advance from the spectrum library is compared with a spectrum of each of the peaks in an actual sample. Thereby, it is possible to reduce the number of spectrum comparisons required for identification, and it is further possible to perform identification quickly since the identification can be performed during analysis.
    Type: Application
    Filed: December 10, 2001
    Publication date: May 30, 2002
    Inventors: Kimihiko Ishii, Yoshiaki Yamada, Kiyotoshi Mori
  • Patent number: 6395456
    Abstract: A semiconductor device achieving higher integration without deterioration of electrical characteristics thereof, a method of manufacturing the semiconductor device, and a method of forming a resist pattern used for that can be obtained. According to the method of forming a resist pattern used for the method of manufacturing a semiconductor device, light is directed via a mask onto a resist film surface formed on a substrate to project a first optical image having a width equal to or less than the wavelength of the light onto the resist surface. The mask is shifted relative to the substrate. Via the shifted mask, light is directed onto the resist film surface to project a second optical image having a width equal to or less than the wavelength of the light onto the resist surface such that the second optical image partially overlaps faith a region where the first optical image is projected.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: May 28, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naohisa Tamada, Yoshiaki Yamada
  • Patent number: 6353786
    Abstract: A vehicle is provided with an electrical motor for driving the vehicle using a battery as a power source. A braking device of the vehicle maximizes the generation of a regenerative braking force of an electrical motor in a range of electricity supplied to the battery, while satisfying the required braking force in response to an applied braking amount.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 5, 2002
    Assignee: Nissan Diesel Co., Ltd.
    Inventors: Yoshiaki Yamada, Jun Yamada
  • Publication number: 20020020922
    Abstract: A sputtering method of depositing a titanium nitride film on a titanium film in contact with a silicon at a bottom of a contact hole is provided, wherein the sputtering method is carried out at a temperature of the silicon region of not less than 450° C., so that the titanium nitride film has a compressive stress of not higher than 5×109 dyne/cm2 whereby the titanium film has such a high stability as preventing any crack upon changing the compressive stress to a tensile stress by a heat treatment.
    Type: Application
    Filed: October 12, 2001
    Publication date: February 21, 2002
    Applicant: NEC Corporation
    Inventors: Yoshiaki Yamada, Takashi Yokoyama
  • Patent number: 6344411
    Abstract: A sputtering method of depositing a titanium nitride film on a titanium film in contact with a silicon at a bottom of a contact hole is provided, wherein the sputtering method is carried out at a temperature of the silicon region of not less than 450° C., so that the titanium nitride film has a compressive stress of not higher than 5×109 dyne/cm2 whereby the titanium film has such a high stability as preventing any crack upon changing the compressive stress to a tensile stress by a heat treatment.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: February 5, 2002
    Assignee: NEC Corporation
    Inventors: Yoshiaki Yamada, Takashi Yokoyama
  • Patent number: 6328122
    Abstract: A hybrid vehicle includes a generator driven by an internal combustion engine, a battery charged by the generator and an electric motor driven by the generator and the battery. A drive system transmits the output of the motor to wheels of the vehicle. When, and only when, adequate power cannot be provided by the motor to the wheels because of a fault, an emergency drive indicator issues a command to a power transmitting mechanism, which is responsive only to the command signal to directly transmit the output of the engine to the drive system.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: December 11, 2001
    Assignee: Nissan Diesel Motor Co., LTD
    Inventors: Yoshiaki Yamada, Jun Yamada, Hiroshi Ienaka
  • Patent number: 6313536
    Abstract: A semiconductor device having a multilayered interconnection structure comprises a wiring pattern (15) composed of a main wiring metal (13) having a forward-tapered shape and a subsidiary wiring metal (14) of a high-melting-point metal formed on side surfaces of the main wiring metal (13). The wiring pattern (15) as a whole has a width substantially equal to that of a bottom end of the main wiring metal (13). After a silicon oxide film (16) is deposited, a through hole (160) is formed in the silicon oxide film (16). The width of the through hole (160) at its bottom is greater and smaller than those of the upper surface and the lower surface of the main wiring metal (13), respectively.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Yoshiaki Yamada
  • Patent number: 6287956
    Abstract: A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Yoshiaki Yamada, Koji Kishimoto
  • Patent number: 6255225
    Abstract: A method of forming a resist pattern and a method of manufacturing a semiconductor device using the method of forming the resist pattern, characterized in that a surface of an organic base coating 3 formed on an etched film 2 is reformed depending on properties of a material of a resist film 4, whereby, in dual processes for forming a lower layer of the organic coating provided to process the etched film, an amount of usable resist is increased and an accuracy of dimensions of the etched film after processing can be improved.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: July 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiaki Yamada, Eiichi Ishikawa
  • Patent number: 6250767
    Abstract: The present invention provides a light guide plate and a surface light source using the light guide plate to improve the utilization efficiency of external light and light from an internal light source and to achieve thinner width of the light guide plate. In this invention, internal light emitted from an internal light source 3 is brought to the inside of the light guide plate 1 from an internal light collecting surface 16 in the light guide plate 1, and external light such as natural light is brought to the inside of the light guide plate 1 from an external light collecting portion 11. The light brought to the inside of the light guide plate reflects and is converged several times from a reflective plate 15 mounted to the outside of the light reflective surface 14 and three side end surfaces 12 and is emitted from the light emissive surface 13 of the light guide plate 1 to a diffusing plate 6.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: June 26, 2001
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Takanari Kusafuka, Masahiro Higuchi, Kenkiti Okamoto, Michiaki Sato, Yoshiaki Yamada, Kenji Kiyota
  • Publication number: 20010003060
    Abstract: A multilevel interconnecting structure includes a plurality of interconnecting layers formed on a semiconductor substrate, a fluorine-doped oxide film for burying portions between the interconnecting layers, and an oxide film formed on the fluorine-doped oxide film, having a planarized surface, and not containing fluorine. A method of forming the multilevel interconnecting structure is also disclosed.
    Type: Application
    Filed: April 23, 1998
    Publication date: June 7, 2001
    Inventors: TAKASHI YOKOHAMA, YOSHIAKI YAMADA, KOJI KISHIMOTO
  • Patent number: 6241857
    Abstract: A substrate is placed in a sputtering apparatus chamber with a surface oriented substantially perpendicularly to a direction along which most particles are released from a target by sputtering. A line perpendicular to the substrate passing through the center of the substrate passes through the center of the target. Pressure in the chamber is adjusted such that the distance between the centers of the substrate and target is shorter than the mean free path of a molecule of the sputtering gas, and the distance between the center of the substrate and target is longer than a diameter of the substrate. The substrate is rotated around an axis perpendicular to the surface of the substrate.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: June 5, 2001
    Assignee: NEC Corporation
    Inventor: Yoshiaki Yamada
  • Patent number: 6241859
    Abstract: The present invention provides a method of forming a silicide layer on a silicon region. The method comprises the following steps. A first refractory metal layer is formed on the silicon region. The first refractory metal layer is made of a first refractory metal. A second refractory metal layer is formed on the first refractory metal layer. The second refractory metal layer is made of a second refractory metal and containing nitrogen. The second refractory metal layer has a film stress of not higher than 1×1010 dyne/cm2. A heat treatment is carried out in a first atmosphere substantially free of nitrogen so as to cause a silicidation of a lower region of the first refractory metal layer, whereby a C49-structured refractory metal silicide layer is formed on the silicon region.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: June 5, 2001
    Assignee: NEC Corporation
    Inventors: Yoshiaki Yamada, Yoshihisa Matsubara, Takashi Ishigami
  • Patent number: 6217319
    Abstract: A hot plate unit includes a cover. The cover includes an inner wall and an outlet. There is provided immediately under the outlet a plate having a ventilation hole. The distance between the plate and a main surface is identical to the distance between the main surface and the internal wall face. The hot plate unit has an displacement control valve for restricting displacement at a level in the range from at least 0.1 L/min to at most 1 L/min.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: April 17, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Miyagi, Yoshiaki Yamada, Takayuki Saito
  • Patent number: 6159756
    Abstract: A semiconductor device is tested without destroying a substrate immediately after a formation of a metal film and before patterning the metal film.To this end, the substrate is first divided into a product region and a test pattern region. Next, an insulating film is formed on the substrate. Thereafter, openings are formed in the insulating film and on the product region and the test pattern region. Subsequently, the metal film is formed in the openings and on the insulating film. Finally, the metal film is patterned to form a wiring pattern.Under these circumstances, a forming state of the metal film in the opening on the test pattern region is actually tested. Specifically, the presence or absence of a void is checked. In accordance with this test result, a forming state of the metal film in the opening in the product region is evaluated.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: December 12, 2000
    Assignee: NEC Corporation
    Inventor: Yoshiaki Yamada
  • Patent number: 6130154
    Abstract: A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: October 10, 2000
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Yoshiaki Yamada, Koji Kishimoto
  • Patent number: 6127267
    Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form a thin and elongated refractory-metal silicide layer while preventing the overgrowth phenomenon. This method is comprised of the steps (a) to (c). In the step (a), a first refractory metal film is formed on a silicon region. In the step (b), a second refractory metal film is formed on the first refractory metal film. The second refractory metal film contains a same refractory metal as the first refractory metal film and nitrogen. A stress of the second refractory metal film is controlled to be a specific value or lower. In the step (c), the first refractory metal film and the second refractory metal film are heat-treated in an atmosphere excluding nitrogen, thereby forming a refractory-metal silicide layer at an interface between the silicon region and the first refractory metal film due to silicidation reaction of the first refractory metal film with the silicon region.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: October 3, 2000
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Takashi Ishigami, Yoshiaki Yamada, Shinichi Watanuki
  • Patent number: 6122049
    Abstract: A flow cell is provided with a cell body having an inlet flow passage, a detection flow passage, an outlet flow passage, and windows fixed to the cell body on both sides of the detection flow passage. The inlet flow passage is formed by inserting in and closely contacting a tube in and to a hole formed in the cell body, respectively.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: September 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yoshimi Sugiyama, Yoshiaki Yamada, Hironori Kaji, Shigeru Amiya
  • Patent number: 6117562
    Abstract: A thermal image transfer recording sodium includes a support and a thermal image transfer ink layer formed on the support. The thermal image transfer ink layer contains a coloring agent, a resin with a melting point of 120.degree. C. or more and an SP value of 10.5 to 12.5, and a melt viscosity lowering material for lowering the melt viscosity of the resin, with the compatibility of the resin and the malt viscosity lowering material, measured by a transparency measurement method, being 0.20 or less, or with the melt viscosity at 150.degree. C. of the thermal image transfer ink layer being in the range of 1.times.10.sup.2 to 5.times.10.sup.6 poise.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: September 12, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Junko Yamaguchi, Mitsuru Maeda, Tetsuji Kunitake, Kazuyoshi Inamura, Yasumitsu Kuga, Shigeru Miyajima, Tadafumi Tatewaki, Yoshiaki Yamada
  • Patent number: 6107190
    Abstract: There is provided a method of fabricating a semiconductor including the steps, in this order, of (a) forming an interlayer insulating film on a semiconductor substrate, (b) forming a first TiN film on the interlayer insulating film by sputtering, (c) forming a hole throughout the interlayer insulating film to thereby cause the semiconductor substrate to appear, (d) forming a second TiN film over the first TiN film by chemical vapor deposition to thereby fill the hole with the second TiN film, and (e) removing the first and second TiN films except TiN filling the hole therewith. When a Ti or TiN film having a thickness sufficient to fill a contact hole or a through-hole therewith is to be formed by CVD even at low temperature, the this method prevents the Ti or TiN film from being cracked or peeled off.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 22, 2000
    Assignee: NEC Corporation
    Inventors: Tetsuya Taguwa, Yoshiaki Yamada