Abstract: A magnetic storage device includes magnetoresistance effect elements. First and second write lines extend along a first direction. Current flows in the first and second write lines only in the first direction and a second direction opposite to the first direction, respectively. A third write line extends along a third direction orthogonal to the first direction. The elements are respectively placed where the first and third write lines cross and the second and third write lines cross. First and second electrodes are provided between the first and third write lines and between the second and third write lines. First and second plugs are respectively connected to the first and second electrodes. The first plug stands at a position apart from the first write line along the third direction. The second plug stands at a position apart from the second write line along the opposite direction to the third direction.

Abstract: A resistance change memory includes a memory cell which is connected to a first node, and programmed from a first resistance state to a second resistance state, a first replica cell which is connected to a second node, generates a write voltage for programming from the first resistance state to the second resistance state, and is fixed in the first resistance state, and a first constant-current source connected to the second node, wherein when writing the second resistance state in the memory cell, a voltage of the first node is held equal to that of the second node.

Abstract: There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a first direction, takes a low-resistance-state having a resistance value lower than that in the high-resistance-state when receiving a write current in a second direction opposite to the first direction, and receives a read current in a read operation, a second magnetoresistive element which takes one of the high-resistance and low-resistance-states in accordance with a magnetization state thereof, is fixed to the low-resistance-state when a direction of the read current is the same as the first direction, and is fixed to the high-resistance-state when the direction of the read current is the same as the second direction, and a control circuit which is connected to the first and second elements, and makes a read voltage applied to the first element equal to that applied to the second element.

Abstract: A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first and third bit lines, and a controller CNT which executes write to a first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and which executes write to a second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.

Abstract: A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.

Abstract: An arrangement is provided in which the durability of an operation changing means is improved when this means is provided to the suspension mechanism in a suspension structure for a work vehicle. A maximum position (A1) and minimum position (A2) of the operation of the suspension mechanism are detected, and an intermediate position (B1) between the maximum and minimum positions (A1) and (A2) is detected. When the intermediate position (B1) departs from the target range (H1), the operation of the suspension mechanism is changed to the body raising side or body lowering side so that the intermediate position (B1) moves toward the target range (H1).

Abstract: A cooling structure for a working vehicle with a transmission disposed rearwardly and downwardly of a driver's seat and having a hydrostatic transmission, and an air-cooled engine disposed rearwardly of the transmission. The cooling structure comprising a fan for cooling the engine and a fan for cooling the transmission mounted on a rotary shaft operatively connecting the transmission with an output shaft of the air-cooled engine, the fans being configured such that air flows generated by the fans move from adjacent the transmission toward the engine; an oil cooler for cooling fluid supplied to the hydrostatic transmission, the oil cooler being disposed between the fan for cooling the engine and the fan for cooling the transmission, and disposed to face each of the fans; and an air guiding plate disposed at a position higher than the oil cooler for guiding air to regions of the fans.

Abstract: A MRAM includes a first magnetoresistive effect (MR) element that takes a low and high resistance states. A second MR element is fixed to a low or high resistance state. First and second MOSFETs are connected to the first and second MR elements, respectively. A sense amplifier amplifies a difference between values of current flowing through the first and second MOSFETs. A current circuit outputs reference current whose value lies between current flowing through the first MR element of the low and high resistance states. A third MOSFET has one end that receives the reference current and is connected to its own gate terminal. The gate terminal of the second MOSFET receives the same potential as the gate terminal of the third MOSFET. A first resistance element is connected to the others end of the third MOSFET and has the same resistance as the second magnetoresistive effect element.

Abstract: A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a second length in a second direction. The second length is equal to or greater than the first length. A ratio of the second length to the first length is a first value. The second magnetoresistive effect element is used to determine a resistance state of the first magnetoresistive effect element. A shape of the second magnetoresistive effect element has a third length in a third direction and a fourth length in a fourth direction. The fourth length is equal to or greater than the third length. A ratio of the fourth length to the third length is a second value which is greater than the first value.

Abstract: A magnetic random access memory includes a memory unit including a memory cell array having a first memory cell for writing first information and a second memory cell for writing second information, and a controller connected to the memory unit, and configured to start supplying a write current in a first direction for writing the first information to the first memory cell and the second memory cell before a write data signal is determined, and, after the write data signal is determined, keep supplying the write current in the first direction to the first memory cell and supply the write current changed in a second direction for writing the second information to the second memory cell alone.

Abstract: A receiving apparatus receives a bitstream that is divided into units encoding a moving picture and includes a stream header indicating how the units are to be decoded. The receiving apparatus estimates the contents of the stream header from the contents of the units, so that decoding of the units can begin before the stream header is received. The receiving apparatus preferably checks for errors in the analysis and decoding of the units, and modifies the estimated stream-header information when an error is discovered. The same unit may be analyzed and decoded repeatedly to hasten the correct estimation of the stream-header information.

Abstract: The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.

Abstract: A magnetic random access memory includes a transistor having a gate electrode formed above a surface of a substrate, and first and second impurity diffusion regions which sandwich a channel region below the gate electrode, a first plug formed on the first impurity diffusion region, a recording element formed on the first plug, including a plurality of stacked layers, and configured to hold information in accordance with an internal magnetization state, a first signal line formed on the recording element, a second plug formed on the second impurity diffusion region, an electrical conductor formed on the second plug, an area of a shape of the electrical conductor, which is projected onto the surface of the substrate, being larger than that of a shape of the recording element, which is projected onto the surface of the substrate, and a second signal line formed on the electrical conductor.

Abstract: A speed-change transmission apparatus for effecting a speed-changing on an engine drive force with utilizing a continuously variable speed-change device, a plurality of planetary transmission mechanisms and a plurality of clutches is constructed to be capable of effecting the speed-changing operation smoothly, regardless of a centrifugal force generated in the clutches. An output from the continuously variable speed-change device and a drive force from the engine are combined by a planetary transmission section. The drive force from this planetary transmission section is transmitted via a clutch section to an output shaft. First, second, third and fourth clutches of the clutch section are configured to be switched over respectively between an engaged condition and a disengaged condition, as clutch members are engaged with or disengaged from output side rotational members.

Abstract: There is provided a magnetic memory device including a first magnetoresistive element which takes a high-resistance-state when receiving a write current in a first direction, takes a low-resistance-state having a resistance value lower than that in the high-resistance-state when receiving a write current in a second direction opposite to the first direction, and receives a read current in a read operation, a second magnetoresistive element which takes one of the high-resistance and low-resistance-states in accordance with a magnetization state thereof, is fixed to the low-resistance-state when a direction of the read current is the same as the first direction, and is fixed to the high-resistance-state when the direction of the read current is the same as the second direction, and a control circuit which is connected to the first and second elements, and makes a read voltage applied to the first element equal to that applied to the second element.

Abstract: A semiconductor memory according to examples of the present invention includes a word line extending in a first direction, first, second and third bit lines extending in a second direction, a first cell unit connected between the first and second bit lines, a second cell unit connected between the first and third bit lines, and a controller CNT which executes write to a first resistance change element under the condition that the word line is made active and potentials of the first and third bit lines are equalized, and which executes write to a second resistance change element under the condition that the word line is made active and potentials of the first and second bit lines are equalized.

Abstract: A magnetic memory includes a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and a word line electrically connected to the magnetoresistive elements. Data erase is performed by setting the magnetization direction of the free layer in a first direction by a magnetic field induced by a current flowing through the word line, and data of the magnetoresistive elements are erased by one time data erase. Data write is performed by setting the magnetization direction of the free layer in a second direction by spin-transfer magnetization reversal by supplying a current in one direction to the magnetoresistive elements.

Abstract: A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the power supply circuit and the write line, and a first register which connects to the write line, receives a logic state of the write line in an input state, stores the received logic state in a storage state, and controls an on/off state of the first pass transistor on the basis of the stored logic state.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.