Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the memory cell based on a current flowing through the bit line, a first switch element which connects the sense amplifier to a drain of the first MOSFET, a second switch element which connects a source of the first MOSFET to the bit line, a third switch element which connects the drain of the first MOSFET to a ground terminal, and a fourth switch element which connects the source of the first MOSFET to a ground terminal.

Abstract: A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

Abstract: A magnetic memory includes a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and a word line electrically connected to the magnetoresistive elements. Data erase is performed by setting the magnetization direction of the free layer in a first direction by a magnetic field induced by a current flowing through the word line, and data of the magnetoresistive elements are erased by one time data erase. Data write is performed by setting the magnetization direction of the free layer in a second direction by spin-transfer magnetization reversal by supplying a current in one direction to the magnetoresistive elements.

Abstract: The refrigerator includes a vegetable compartment (107) thermally insulated by a rear partition (111), and a mist generation department (139) for atomizing a mist into the vegetable compartment (107), and the mist generation department (139) includes a atomizing electrode (135) for atomizing the mist into the vegetable compartment (107), a voltage applicator (133) for applying a voltage to the atomizing electrode (135), and a cooling pin (134) coupled to the atomizing electrode (135), in which the atomizing electrode (135) is cooled to a temperature lower than the dew point by a outlet air-duct for freezer compartment (141), and the moisture in the air is cooled to condense dew on the atomizing electrode (135), and is atomized as a mist into the vegetable compartment (107), and dew can be condensed from moisture onto the atomizing electrode (135) stably and in a simple configuration, and the freshness of the food is enhanced while the reliability of the refrigerator is enhanced.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: A plurality of memory cells, each including a variable resistance element capable of having four or more values, are arranged at intersections of first wirings and second wirings. A control circuit selectively drives the first and second wirings. A sense amplifier circuit compares, with a reference voltage, a voltage generated by a current flowing through a selected memory cell. A reference voltage generation circuit includes: a resistance circuit including first and second resistive elements connected in parallel. Each of the first resistive elements has a resistance value substantially the same as a maximum resistance value in the variable resistance elements, and each of the second resistive elements has a resistance value substantially the same as a minimum resistance value in the variable resistance elements. A current regulator circuit averages currents flowing through the first and second resistive elements.

Abstract: The apparatus includes a hydrostatic stepless speed change section 20 receiving an output of an engine 1, a planetary transmission section 3a having a plurality of planetary transmission mechanisms PF, PR and a plurality of output members 41, 42, the planetary transmission section being configured to combine a drive force outputted from the hydrostatic stepless speed change section 20 and an engine drive force that has not been subjected to any speed change action by the hydrostatic stepless speed change section 20, and a speed change output section 3b having an output shaft 70, the speed change output section being configured to output combined drives force outputted from the plurality of output members 41, 42 in a plurality of different speed ranges from the output shaft 70.

Abstract: A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1?m?n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

Abstract: There is provided a document use tracking system including a use history recording unit that records, for each document stored in a document storage unit, a use history record for each user about each element in the document, a search condition reception unit that receives an input of a search condition, an element score calculation unit that calculates, for each element of each document, an element score indicating closeness of fit of the element for the search condition, an importance score calculation unit that calculates, for each combination of an element and a user who has performed an operation, an importance score based on the element score of the element and the use history record of the user for the element, and a monitored object information presentation unit that presents the importance score calculated by the importance score calculation unit and the user corresponding to the importance score.

Abstract: A dust removal system for a riding lawn mower, comprising an engine, a speed change device disposed outside of an engine compartment, and a universal coupling inserted through an opening provided to a separating wall in order to connect an output shaft of the engine and an input shaft of the speed change device. The dust removal system is composed of a perforated board which rotates integrally with the output shaft and around the axis of the output shaft in order to impede grass cuttings from flowing into the engine compartment through the opening, the perforated board having an insertion hole formed in the center to allow the universal coupling to be inserted; and a seal unit for substantially sealing the space between the universal coupling and the peripheral edge of the insertion hole. The seal unit has a radially extending flange formed on the universal coupling, and a ring member in which one end is mounted on the flange and the other end is in contact with the peripheral area around the insertion hole.

Abstract: An endoscope comprises: an insertion tube to be inserted into a body cavity, the insertion tube including a hard distal end portion, a curving portion continuous with the hard distal end portion, and a flexible portion continuous with the curving portion; a contained part of the insertion tube which is accommodated at least inside the curving portion; and at least one movement regulating member which extends inside the curving portion and adapted to regulate at least radial movement of the contained part, one end portion of the position regulating member passing through a rear connecting portion connecting the curving portion and the flexible portion to extend to the flexible portion side, a section of a portion of the movement regulating member inserted into the flexible portion from the rear connecting portion being smaller than a section of a portion of the movement regulating member within the curving portion.

Abstract: A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.

Abstract: A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the power supply circuit and the write line, and a first register which connects to the write line, receives a logic state of the write line in an input state, stores the received logic state in a storage state, and controls an on/off state of the first pass transistor on the basis of the stored logic state.

Abstract: A semiconductor memory device comprises a plurality of cell arrays, each cell array including a plurality of mutually parallel word lines, a plurality of mutually parallel bit lines disposed to cross these word lines, and a plurality of cells connected to the intersections of these word lines and bit lines, respectively, one portion of the cell arrays forming a memory cell array that has the cells as memory cells, and another portion of the cell arrays forming a reference cell array that has the cells as reference cells. A cell selection circuit is operative to select from the memory cell array a memory cell whose data is to be read, and to select from the reference cell array a reference cell at a position corresponding to a position of the memory cell selected in the memory cell array. A sense amplifier circuit is operative to detect and compare a current or a voltage of the selected memory cell with a current or a voltage of the selected reference cell, and thereby read data of the memory cell.

Abstract: A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.

Abstract: A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

Abstract: A cooling structure for a working vehicle with a transmission disposed rearwardly and downwardly of a driver's seat and having a hydrostatic transmission, and an air-cooled engine disposed rearwardly of the transmission. The cooling structure comprising a fan for cooling the engine and a fan for cooling the transmission mounted on a rotary shaft operatively connecting the transmission with an output shaft of the air-cooled engine, the fans being configured such that air flows generated by the fans move from adjacent the transmission toward the engine; an oil cooler for cooling fluid supplied to the hydrostatic transmission, the oil cooler being disposed between the fan for cooling the engine and the fan for cooling the transmission, and disposed to face each of the fans; and an air guiding plate disposed at a position higher than the oil cooler for guiding air to regions of the fans.

Abstract: A composite planetary transmission section (P) is provided for synthesizing output from a stepless speed changing section (20) with an engine drive force. In a transmission line from the planetary transmission section (P) to an output rotational body (90), there are provided first clutch mechanism (60), a second clutch mechanism (70), a speed-reducing planetary transmission mechanism (80), an operable coupling clutch mechanism (110) and an output clutch mechanism (120). A ring gear (83) of the speed-reducing planetary transmission mechanism (80) includes a brake mechanism (100). A sun gear (43) of the planetary transmission section (P), an input side rotational member (62) of the first clutch mechanism (60), an input side rotational member (71) of the second clutch mechanism (70), a sun gear (84) of the speed-reducing planetary transmission mechanism (80), and an input side rotational member (122) of the output clutch mechanism (120) are rotatable about a common rotational axis.

Abstract: A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.