Patents by Inventor Yoshihiro Ueda

Yoshihiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120307863
    Abstract: An exhaust gas temperature detection sensor is arranged at a predetermined position outside a muffler, or at a predetermined position outside an exhaust pipe constituting an exhaust gas flow passage on a more downstream side than the muffler in an exhaust direction. The sensor detects that an atmosphere temperature at the predetermined position outside the muffler has reached a predetermined temperature based on an increase in a temperature inside the muffler, or detects that an atmosphere temperature at the predetermined position outside the exhaust pipe has reached a predetermined temperature based on an increase in a temperature of an exhaust gas inside the exhaust pipe.
    Type: Application
    Filed: March 15, 2012
    Publication date: December 6, 2012
    Applicant: KUBOTA CORPORATION
    Inventors: Hiroyuki TADA, Masato ASAHARA, Yoshihiro UEDA, Hideki AOKI, Akira MINOURA
  • Patent number: 8307143
    Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: November 6, 2012
    Assignee: d-broad, Inc.
    Inventors: Katsuhiro Hirayama, Hiroto Yoshikawa, Yoshihiro Ueda, Osamu Mikami
  • Patent number: 8277528
    Abstract: A dust removal system for a riding lawn mower, comprising an engine, a speed change device disposed outside of an engine compartment, and a universal coupling inserted through an opening provided to a separating wall in order to connect an output shaft of the engine and an input shaft of the speed change device. The dust removal system is composed of a perforated board which rotates integrally with the output shaft and around the axis of the output shaft in order to impede grass cuttings from flowing into the engine compartment through the opening, the perforated board having an insertion hole formed in the center to allow the universal coupling to be inserted; and a seal unit for substantially sealing the space between the universal coupling and the peripheral edge of the insertion hole. The seal unit has a radially extending flange formed on the universal coupling, and a ring member in which one end is mounted on the flange and the other end is in contact with the peripheral area around the insertion hole.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 2, 2012
    Assignee: Kubota Corporation
    Inventors: Hideya Umemoto, Eiji Satou, Takeshi Komorida, Yoshihiro Ueda, Masato Asahara, Kazuhiro Ochi, Masahiro Yamada
  • Publication number: 20120243297
    Abstract: According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and third bit lines, a second transistor and a second memory element between the second and third bit lines. Control terminals of the first and second transistors are connected to the word line. The resistance states of the first and second memory elements change to the first or second resistance state in accordance with a write pulse.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 27, 2012
    Inventors: Akira KATAYAMA, Yoshihiro Ueda
  • Publication number: 20120230090
    Abstract: A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Takahashi, Yoshihiro Ueda
  • Publication number: 20120224412
    Abstract: A memory includes memory cells each storing data according to a change in a resistance state, and reference cells referred to in order to detect data stored in the memory cells. Sense amplifiers compare reference data in the reference cells with data in the memory cells to detect the data in the memory cells. A counter counts a number NH of the memory cells having a resistance higher than a resistance of each reference cell or a number NL of the memory cells having a resistance lower than the resistance of each reference cell based on a result of detecting first logical data stored in the memory cells using each reference cell storing the first logical data. A determining part determines one of the reference cells as an optimum reference cell used in an actual data reading operation based on the number NH or NL for the reference cells.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 6, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshihiro Ueda
  • Publication number: 20120215404
    Abstract: A content management section rearranges contents in an order from a content having a greater information value, preparing a content list. With respect to assignable areas of a display apparatus, a region value is compared with an information value of each content; the content may be assigned to the area when the information value exceeds the region value. The contents are associated with information values and the areas are associated with region values; thus, the content can be assigned to the area that is more suitable. When there are several assignable areas, a target content is assigned to an area having a highest region value.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 23, 2012
    Applicant: DENSO CORPORATION
    Inventors: Hitoshi Sugiyama, Shigeo Katoh, Yoshihiro Ueda
  • Patent number: 8223565
    Abstract: A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda
  • Publication number: 20120155146
    Abstract: According to one embodiment, a resistance-change memory includes memory cells between a bit line and a source line, each of the memory cells including a memory element and a cell transistor having a gate connected to a word line, an n-channel transistor having a gate to which a first control voltage is applied, and a current path connected to the bit line, and a p-channel transistor having a gate to which a second control voltage is applied, and a current path connected to the source line. When the memory cell is read, the potential of the bit line is controlled by the first control voltage, and the potential of the source line is controlled by the second control voltage.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 21, 2012
    Inventors: Yoshihiro UEDA, Kenji Tsuchida
  • Patent number: 8199597
    Abstract: First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda
  • Publication number: 20120137720
    Abstract: In a storage compartment (124), storage spaces having different mist concentrations are formed such that effects of a mist is more efficiently utilized to provide a refrigerator with improved usability. The storage compartment (124) includes a first storage unit (164) that has a high mist concentration. The first storage unit (164) includes a spray device (167) and is disposed in a position outside an air path of cool air between a discharge port (152) through which the cool air flows in from outside the storage compartment (124) and a suction port (149) through which the cool air is discharged to outside the storage compartment (124). Thus, mist concentration inside the first storage unit (164) can be increased.
    Type: Application
    Filed: August 26, 2010
    Publication date: June 7, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshihiro Ueda, Satomi Ueda, Atsuhiro Ueda, Motohiro Ueda, Toyoshi Kamisako, Kenichi Kakita, Kumiko Okubo, Mitoko Ishita
  • Publication number: 20120137711
    Abstract: To maintain an appropriate humidity in a refrigerator using a spray device to spray mist, without depending on a moisture sensor. A refrigerator (100) for forcibly circulating cold air which is gas cooled in a cooling compartment (110), the refrigerator including: a first storage compartment (107) disposed on the way of an air passage; a spray device (131) which sprays mist into the first storage compartment (107); a damper (145) disposed upstream of the first storage compartment (107); a delay unit (156) which generates, based on an open signal issued when the damper (145) is opened, a first signal for stopping the operation of the spray device (131) after an elapse of a first time period, and to generate, based on a close signal issued when the damper (145) is closed, a second signal for starting the operation of the spray device (131) after an elapse of a second time period; and a control unit (146) which controls the spray device (131).
    Type: Application
    Filed: August 24, 2010
    Publication date: June 7, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kenichi Kakita, Toshiaki Mamemoto, Yoshihiro Ueda
  • Patent number: 8189363
    Abstract: A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Tsuchida, Yoshihiro Ueda
  • Patent number: 8172714
    Abstract: A composite planetary transmission section (P) is provided for synthesizing output from a stepless speed changing section (20) with an engine drive force. In a transmission line from the planetary transmission section (P) to an output rotational body (90), there are provided first clutch mechanism (60), a second clutch mechanism (70), a speed-reducing planetary transmission mechanism (80), an operable coupling clutch mechanism (110) and an output clutch mechanism (120). A ring gear (83) of the speed-reducing planetary transmission mechanism (80) includes a brake mechanism (100). A sun gear (43) of the planetary transmission section (P), an input side rotational member (62) of the first clutch mechanism (60), an input side rotational member (71) of the second clutch mechanism (70), a sun gear (84) of the speed-reducing planetary transmission mechanism (80), and an input side rotational member (122) of the output clutch mechanism (120) are rotatable about a common rotational axis.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 8, 2012
    Assignee: Kubota Corporation
    Inventors: Shoso Ishimori, Yoshiyuki Katayama, Yoshihiro Ueda, Shinichi Morita, Shinichi Kawabata, Shigeki Hayashi, Masaaki Nishinaka, Takayasu Kobayashi, Go Takagi
  • Publication number: 20120069629
    Abstract: According to one embodiment, a semiconductor memory device includes a first reference cell being arranged in a first cell array, and a plurality of first fuse cells being arranged in the first cell array. The first reference cell and the plurality of first fuse cells are arranged on the same row or column.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Inventors: Yoshihiro UEDA, Akira KATAYAMA, Ryousuke TAKIZAWA
  • Publication number: 20120063215
    Abstract: A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
    Type: Application
    Filed: July 27, 2011
    Publication date: March 15, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiro TAKAHASHI, Katsuyuki Fujita, Yoshihiro Ueda, Katsuhiko Hoya
  • Publication number: 20120063216
    Abstract: A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
    Type: Application
    Filed: August 8, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki Fujita, Yoshihiro Ueda
  • Publication number: 20120057620
    Abstract: A radio communication system of the present invention comprises a radio communication device which transmits or receives a first beacon signal and a second beacon signal. A beacon transmission radio communication device transmits the first beacon signal in a preset timing pattern P1, while a beacon signal reception radio communication device receives the first beacon signal in a preset timing pattern P2. The beacon transmission radio communication device transmits the second beacon signal upon a passage of a delay time period R which is shorter than a standby time period Q which is shorter than the timing pattern P1, after the standby time period Q has passed. The beacon signal reception radio communication device attempts to receive the second beacon signal according to a passage of the delay time period R which is shorter than the standby time period Q which is shorter than the timing pattern P2, after the standby time period Q has passed.
    Type: Application
    Filed: July 14, 2010
    Publication date: March 8, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiro Yamamoto, Yoshihiro Ueda, Yoshio Horiike
  • Patent number: 8117813
    Abstract: A riding type grass mower includes a right wheel and a left wheel, a rear-discharge type mower unit disposed forwardly of the right/left wheels, a driver's seat disposed between and upwardly of the right/left wheels, an engine mounted rearwardly of the driver's seat, an engine hood for covering the engine, and a restricting unit disposed rearwardly of the driver's seat and at an area downwardly of the engine hood, the restricting unit having a restricting face (including a mesh face) configured to restrict upward rising of cut grass discharged from the mower unit.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 21, 2012
    Assignee: Kubota Corporation
    Inventors: Akihito Sugio, Osami Fujiwara, Yusuke Shoji, Yoshihiro Ueda
  • Patent number: 8116150
    Abstract: A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda