Abstract: According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

Abstract: A display control apparatus that assigns display target contents to a plurality of areas configured as display areas in a screen of a display apparatus mounted on a vehicle is provided. The display control apparatus comprises a content manager for managing the contents in association with content information indicating attributes of the contents, an area manager for managing the areas in association with area information indicating attributes of the areas, and a content assignment controller for generating a content list listing the contents and determining content-area combinations based on the content information and the area information in an order of the content list.

Abstract: A display control apparatus for controlling a display device including a screen having a plurality of areas so as to assign and display a content on a corresponding area, includes: a content managing unit managing the content by associating content information; an area managing unit managing the area by associating area information; and a content assignment control unit determining a combination of the content and the area. The content assignment control unit generates a content list, generates an area list, extracts a combination list based on the area list and the content list, calculates an evaluation reference value of each combination list based on the content information and the area information, selects the combination list based on the evaluation reference value of each combination list, and determines a combination.

Abstract: A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.

Abstract: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.

Abstract: In a video distribution apparatus, a memory caches segments of video data into which video data received from a communication network is sectioned on a basis of a predetermined unit and stores video identifying information of the segments of video data. A distribution controller derives, upon receipt of a cache distribution request from the network, video identifying information contained in a cache distribution request. A relay controller obtains segments of video data associated with the video identifying information from the memory to transfer the obtained segments of video data to a requester at a transfer rate defined on the segments of video data in the vicinity of a source of the video data. The video can be distributed at a transfer rate close to a transfer rate defined by a content distribution server while the video traffic can be diminished.

Abstract: A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell.

Abstract: According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

Abstract: A content management section rearranges contents in an order from a content having a greater information value, preparing a content list. With respect to assignable areas of a display apparatus, a region value is compared with an information value of each content; the content may be assigned to the area when the information value exceeds the region value. The contents are associated with information values and the areas are associated with region values; thus, the content can be assigned to the area that is more suitable. When there are several assignable areas, a target content is assigned to an area having a highest region value.

Abstract: Positional relationship among the first link support shaft (85), the second link support shaft (86), the first arm support shaft (88) and the second arm support shaft (89) is set such that an upper portion of the first lift link (81) comes into substantial agreement with a rear end of the machine body (1), when the upper free end of the first lift link (81) is pivoted maximally rearward in the course of transition of the arm (77) from a lowermost state realized lifting down the arm (77) to an uppermost state realized by lifting up the arm (77).

Abstract: A memory includes storage elements, a signal holding part and a sense amplifier. A driving-method includes a read operation for reading target data stored in a first storage element of the storage elements. In the read operation, the signal holding part holds a first voltage according to the target data. First sample data of a first logic is written to the first storage element. The signal holding part holds a second voltage according to the first sample data. Second sample data of a second logic opposite to the first logic is written to the first storage element. The signal holding part holds a third voltage according to the second sample data. The sense amplifier compares a read signal based on the first voltage with a reference signal generated based on the second and third voltages to detect a logic of the target data stored in the first storage element.

Abstract: In a memory, a signal holder holds voltages according to data in the storage elements. A busy-signal controller controls a busy-signal. The busy-signal determines whether to permit or reject reception of a read/write enable signal. During reception of the read/write enable signal is rejected, the signal holder holds a first to a third voltages. The first voltage corresponds to target data stored in a first storage element. The second voltage corresponds to first sample data of first logic written to the first storage element. The third voltage corresponds to second sample data of second logic. A sense amplifier detects logic of the target data by comparing a read signal of the first voltage with a reference signal generated by the second and third voltages. The write driver writes the target data/write data to the first storage element. After writing, the reception of the read/write enable signal is permitted.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ?|Ic+/Ic?|?1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Ic? and a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to Ic+.

Abstract: According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

Abstract: A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.

Abstract: A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

Abstract: A riding mower having left and right driving rear wheels independently drivable forward and backward and a pair of left and right steerable front wheels is provided with a support device capable of being mounted with a cylindrical gas cylinder in a horizontal position on an external side of a rollover projection frame. The support device is provided such that the mounted gas cylinder is positioned along front and rear of the rollover protection frame and is mounted in a tilted state in which the central axis of the cylindrical gas cylinder is closer to a central side in a lateral direction of a vehicle body toward a rear side from a plan view.

Abstract: A hydraulic system of a work machine with a hydraulically controlled implement includes: an operating oil flow passage for flowing operating oil from a main pump; a boost flow oil passage for supplying operating oil to the operating oil flow passage; a connection unit for connecting the implement which is provided downstream of the confluence on the operating oil flow passage; a controller for controlling the high-flow valve; and a high-flow switch which is connected to the controller and is configured to effect or cancel a command of the amount increase on a high-flow valve. Annunciation is made when the connection unit is connected to a high-flow actuator for the implement requiring an amount increase of the operating oil, and the amount increase is effected by the high-flow valve in accordance with an operation of the high-flow switch.

Abstract: A hood for a loader work machine is provided at the rear end of the frame body and downwardly of the transverse connecting member between the pair of right/left support frame members. The transverse connecting member includes a front wall plate and an upper wall plate projecting rearward from an upper end of the front wall plate. The upper wall plate of the transverse connecting member is disposed more downwardly than the vertical center of the cabin. A rear portion of the upper wall plate is inclined downwardly rearward. A hood upper wall is provided for covering a rear upper side between the pair of right/left support frame members. A front end portion of the hood upper wall is connected to the rear portion of the upper wall plate of the transverse connecting member. The hood upper wall is inclined downwardly rearward in correspondence with the rear portion of the upper wall plate.

Abstract: A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell.