Patents by Inventor Yoshitaka Tsunashima

Yoshitaka Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080224252
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Application
    Filed: February 8, 2008
    Publication date: September 18, 2008
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Patent number: 7425480
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: September 16, 2008
    Assignee: Kabushiki Kaisha Tohisba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Publication number: 20080211004
    Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 4, 2008
    Inventors: Yoshio OZAWA, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
  • Patent number: 7372113
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20080102616
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Application
    Filed: December 7, 2007
    Publication date: May 1, 2008
    Inventors: Yoshitaka Tsunashima, Seiji Ihumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Patent number: 7361960
    Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: April 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kiyotaka Miyano, Yukihiro Ushiku
  • Publication number: 20080003771
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Application
    Filed: June 19, 2007
    Publication date: January 3, 2008
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7312138
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Patent number: 7306994
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: December 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Patent number: 7303946
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: December 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Patent number: 7282774
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: October 16, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20070218605
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Application
    Filed: April 23, 2007
    Publication date: September 20, 2007
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Publication number: 20070218606
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Application
    Filed: April 23, 2007
    Publication date: September 20, 2007
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Publication number: 20070215958
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: May 15, 2007
    Publication date: September 20, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20070200168
    Abstract: A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control gate electrode is further formed thereon. A thickness of the tunnel insulating layer is set to be 4 to 10 nm, and data writing/data erasing operations are carried out by making an F-N tunneling current flow in the tunnel insulating layer.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 30, 2007
    Inventors: Yoshio Ozawa, Yoshitaka Tsunashima
  • Publication number: 20070172997
    Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.
    Type: Application
    Filed: March 9, 2007
    Publication date: July 26, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
  • Patent number: 7235456
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7208797
    Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
  • Patent number: 7145667
    Abstract: There is here disclosed a semiconductor device manufacturing method, comprising arranging at least one subject piece in a processing chamber, and starting a predetermined processing, applying a light having a predetermined wavelength to a monitoring section which is formed to enable transmission and reflection of the light and which is provided at a tip of a monitoring device to indirectly monitor a thickness of a film on the subject piece, and measuring a reflection light which is the application light is reflected near the monitoring section, while the light and the reflection light are isolated from an atmosphere and a substance in the chamber, measuring an amount of a substance on the monitoring section based on the reflection light, determining a thickness of a film on the subject piece based on the substance, and conducting the processing while controlling the processing based on the thickness of the film.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihito Yamamoto, Takashi Nakao, Yuuichi Mikata, Yoshitaka Tsunashima
  • Publication number: 20060270170
    Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.
    Type: Application
    Filed: September 16, 2005
    Publication date: November 30, 2006
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima