Patents by Inventor Yoshitaka Tsunashima

Yoshitaka Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040251521
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: July 1, 2004
    Publication date: December 16, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20040248393
    Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
    Type: Application
    Filed: June 16, 2004
    Publication date: December 9, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuaki Nakajima, Yoshitaka Tsunashima, Takayuki Ito, Kyoichi Suguro
  • Patent number: 6794713
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Patent number: 6790723
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20040171252
    Abstract: An improved method of reducing contamination in processing of ICs is disclosed. The method includes forming a contamination protection layer on at least the back surface of the substrate. The contamination protection layer comprises a low diffusion factor and can be cleaned efficiently. In one embodiment, the contamination protection layer comprises HCD silicon nitride.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Haoren Zhuang, Katsuaki Natori, Gerhard Beitel, Bum-ki Moon, Moto Yabuki, Yoshitaka Tsunashima, Karl Hornik
  • Patent number: 6784508
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Patent number: 6774462
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: August 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Patent number: 6772045
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Patent number: 6767796
    Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: July 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuaki Nakajima, Yoshitaka Tsunashima, Takayuki Ito, Kyoichi Suguro
  • Publication number: 20040070045
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Application
    Filed: July 22, 2003
    Publication date: April 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Patent number: 6713359
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: March 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Publication number: 20040041179
    Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.
    Type: Application
    Filed: September 5, 2003
    Publication date: March 4, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ichiro Mizushima, Shigehiko Saida, Takeo Furuhata, Yoshitaka Tsunashima
  • Publication number: 20030222318
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: October 24, 2002
    Publication date: December 4, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20030211713
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Application
    Filed: April 4, 2003
    Publication date: November 13, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Publication number: 20030173617
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
  • Patent number: 6617226
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoioni Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Patent number: 6600189
    Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: July 29, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Junichiro Iba
  • Publication number: 20030139835
    Abstract: A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.
    Type: Application
    Filed: August 30, 2002
    Publication date: July 24, 2003
    Inventors: Shuji Katsui, Masayuki Tanaka, Masaki Kamimura, Hiroshi Akahori, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Shigehiko Saida, Yoshitaka Tsunashima, Yuuichi Mikata
  • Publication number: 20030127640
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Application
    Filed: March 21, 2002
    Publication date: July 10, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Patent number: 6570217
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano