Patents by Inventor Yoshitaka Tsunashima

Yoshitaka Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6552380
    Abstract: A deep trench is formed in a silicon substrate. The inner surface of the trench is next coated with a thin polycrystalline silicon film (liner film) so as not to close the trench. A silicon germanium film (node electrode) is then formed on the thin polycrystalline silicon film so as not to close the trench. Next, a heat treatment is performed on the silicon germanium film thereby to flow only the silicon germanium so that the trench is filled.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: April 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima
  • Patent number: 6538271
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: March 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20030045960
    Abstract: There is here disclosed a semiconductor device manufacturing method, comprising arranging at least one subject piece in a processing chamber, and starting a predetermined processing, applying a light having a predetermined wavelength to a monitoring section which is formed to enable transmission and reflection of the light and which is provided at a tip of a monitoring device to indirectly monitor a thickness of a film on the subject piece, and measuring a reflection light which is the application light is reflected near the monitoring section, while the light and the reflection light are isolated from an atmosphere and a substance in the chamber, measuring an amount of a substance on the monitoring section based on the reflection light, determining a thickness of a film on the subject piece based on the substance, and conducting the processing while controlling the processing based on the thickness of the film.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 6, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihito Yamamoto, Takashi Nakao, Yuuichi Mikata, Yoshitaka Tsunashima
  • Publication number: 20020171099
    Abstract: A deep trench is formed in a silicon substrate. The inner surface of the trench is next coated with a thin polycrystalline silicon film (liner film) so as not to close the trench. A silicon germanium film (node electrode) is then formed on the thin polycrystalline silicon film so as not to close the trench. Next, a heat treatment is performed on the silicon germanium film thereby to flow only the silicon germanium so that the trench is filled.
    Type: Application
    Filed: July 5, 2002
    Publication date: November 21, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima
  • Publication number: 20020086486
    Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
    Type: Application
    Filed: October 11, 2001
    Publication date: July 4, 2002
    Inventors: Masayuki Tanaka, Kazuaki Nakajima, Yoshitaka Tsunashima, Takayuki Ito, Kyoichi Suguro
  • Patent number: 6383837
    Abstract: A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A photodetector detects the laser beam output from the stacked chips through the alignment holes in these chips. The positions of the chips are so controlled that the amount of the light detected by this photodetector is a maximum.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 7, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshitaka Tsunashima
  • Patent number: 6376888
    Abstract: Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the m
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: April 23, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kyoichi Suguro, Atsushi Murakoshi, Kouji Matsuo, Toshihiko Iinuma
  • Publication number: 20020045296
    Abstract: A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
    Type: Application
    Filed: December 21, 2001
    Publication date: April 18, 2002
    Applicant: Kabushika Kaisha Toshiba
    Inventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
  • Publication number: 20020028532
    Abstract: A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A photodetector detects the laser beam output from the stacked chips through the alignment holes in these chips. The positions of the chips are so controlled that the amount of the light detected by this photodetector is a maximum.
    Type: Application
    Filed: April 28, 2000
    Publication date: March 7, 2002
    Inventor: Yoshitaka Tsunashima
  • Publication number: 20020024119
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: October 30, 2001
    Publication date: February 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20020024082
    Abstract: A buried strap is formed after forming an SiC layer on the side surface of a trench in order to suppress the epitaxial growth of Si from the side surface (single crystal Si) of the trench to the buried strap (polycrystalline Si) without causing an increase in the contact resistance in the post process accompanied by high temperature after formation of the buried strap.
    Type: Application
    Filed: October 26, 2001
    Publication date: February 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura, Masayuki Tanaka, Shigehiko Saida, Hirofumi Inoue, Takeshi Hamamoto
  • Patent number: 6346438
    Abstract: A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
  • Patent number: 6335251
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Patent number: 6333547
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6326658
    Abstract: A buried strap is formed after forming an SiC layer on the side surface of a trench in order to suppress the epitaxial growth of Si from the side surface (single crystal Si) of the trench to the buried strap (polycrystalline Si) without causing an increase in the contact resistance in the post process accompanied by high temperature after formation of the buried strap.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura, Masayuki Tanaka, Shigehiko Saida, Hirofumi Inoue, Takeshi Hamamoto
  • Patent number: 6313047
    Abstract: Disclosed is an MOCVD method of forming a tantalum oxide film. First, water vapor used as an oxidizing agent is supplied into a process container to cause moisture to be adsorbed on a surface of each semiconductor wafer. Then, PET gas used as a raw material gas is supplied into the process container and is caused to react with the moisture on the wafer at a process temperature of 200° C., thereby forming an interface layer of tantalum oxide. Then, PET gas and oxygen gas are supplied into the process container at the same time, and are caused to react with each other at a process temperature of 410° C., thereby forming a main layer of tantalum oxide on the interface layer.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: November 6, 2001
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Yuichiro Morozumi, Dong-Kyun Choi, Takuya Sugawara, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20010027031
    Abstract: Disclosed is an MOCVD method of forming a tantalum oxide film. First, water vapor used as an oxidizing agent is supplied into a process container to cause moisture to be adsorbed on a surface of each semiconductor wafer. Then, PET gas used as a raw material gas is supplied into the process container and is caused to react with the moisture on the wafer at a process temperature of 200° C., thereby forming an interface layer of tantalum oxide. Then, PET gas and oxygen gas are supplied into the process container at the same time, and are caused to react with each other at a process temperature of 410° C., thereby forming a main layer of tantalum oxide on the interface layer.
    Type: Application
    Filed: March 20, 2001
    Publication date: October 4, 2001
    Inventors: Kazuhide Hasebe, Yuichiro Morozumi, Dong-Kyun Choi, Takuya Sugawara, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20010024867
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Application
    Filed: June 6, 2001
    Publication date: September 27, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20010023108
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Application
    Filed: April 3, 2001
    Publication date: September 20, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Publication number: 20010023120
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 20, 2001
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka