Patents by Inventor Yoshitaka Tsunashima

Yoshitaka Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060244083
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Application
    Filed: June 28, 2006
    Publication date: November 2, 2006
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Patent number: 7129132
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 31, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 7101775
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: September 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Patent number: 7098115
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20060131651
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Application
    Filed: January 27, 2006
    Publication date: June 22, 2006
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7060555
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 7041584
    Abstract: An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuaki Nakajima, Yoshitaka Tsunashima, Takayuki Ito, Kyoichi Suguro
  • Patent number: 7019364
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 6989316
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Patent number: 6989281
    Abstract: A cleaning method for a semiconductor device manufacturing apparatus includes a process of forming a film on a subject piece in a processing chamber, applying light having a predetermined wavelength to a monitoring section to indirectly monitor a thickness of a film formed on the subject piece, introducing cleaning gas capable of removing a substance deposited on the monitoring section into the processing chamber, measuring a reflection light which is the application light reflected near the monitoring section, measuring an amount of a substance corresponding to a thickness of a film deposited on the monitoring section based on a measurement result of the reflection light; and introducing, into the processing chamber, a cleaning gas which can remove the substance on the monitoring section until a measurement value of the amount of the substance on the monitoring section becomes zero.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihito Yamamoto, Takashi Nakao, Yuuichi Mikata, Yoshitaka Tsunashima
  • Publication number: 20050170666
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using ND3 gas.
    Type: Application
    Filed: December 1, 2004
    Publication date: August 4, 2005
    Inventors: Katsuyuki Sekine, Yoshitaka Tsunashima, Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Kazuhiro Eguchi
  • Publication number: 20050158932
    Abstract: A method of manufacturing a semiconductor device, comprises: providing a gate insulation layer of a high dielectric constant containing a metal element on a surface of a semiconductor substrate, part of which becoming a channel; providing a first conductive layer containing a silicon element on the surface of said gate insulation layer, said first conductive layer being a gate electrode; and introducing nitrogen or oxygen onto an interface between said gate insulation layer and said first conductive layer by executing a thermal treatment upon said semiconductor substrate in a atmosphere containing a nitriding agent or an oxidizing agent.
    Type: Application
    Filed: November 24, 2004
    Publication date: July 21, 2005
    Inventors: Seiji Inumiya, Akio Kaneko, Motoyuki Sato, Katsuyuki Sekine, Kazuhiro Eguchi, Yoshitaka Tsunashima
  • Patent number: 6893928
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
  • Publication number: 20050059203
    Abstract: A cleaning method for a semiconductor device manufacturing apparatus includes a process of forming a film on a subject piece in a processing chamber, applying light having a predetermined wavelength to a monitoring section to indirectly monitor a thickness of a film formed on the subject piece, introducing cleaning gas capable of removing a substance deposited on the monitoring section into the processing chamber, measuring a reflection light which is the application light reflected near the monitoring section, measuring an amount of a substance corresponding to a thickness of a film deposited on the monitoring section based on a measurement result of the reflection light; and introducing, into the processing chamber, a cleaning gas which can remove the substance on the monitoring section until a measurement value of the amount of the substance on the monitoring section becomes zero.
    Type: Application
    Filed: October 5, 2004
    Publication date: March 17, 2005
    Inventors: Akihito Yamamoto, Takashi Nakao, Yuuichi Mikata, Yoshitaka Tsunashima
  • Patent number: 6844234
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: January 18, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20050006675
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Application
    Filed: August 11, 2004
    Publication date: January 13, 2005
    Inventors: Yoshitaka Tsunashima, Seiji Ihumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20050006674
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Application
    Filed: August 5, 2004
    Publication date: January 13, 2005
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Publication number: 20040266176
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20040266177
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Publication number: 20040259386
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 23, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima