Patents by Inventor Yoshitaka Tsunashima

Yoshitaka Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6284583
    Abstract: A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: September 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 6278164
    Abstract: A p-type silicon substrate has an element isolation region of an STI structure formed therein. A transistor region isolated by the isolation region has a n-type source/drain diffusion layer. Further, a p-channel impurity layer is formed substantially only in its channel region for controlling its threshold voltage (Vth). A gate insulator film consisting of a high dielectric film is formed on the channel region with an Si3N4 film interposed therebetween. A metal gate electrode having its bottom and side surfaces covered with the gate insulator film is provided in a self-alignment manner with respect to the source/drain diffusion layer.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: August 21, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Yoshitaka Tsunashima, Keitaro Imai, Tomonori Aoyama
  • Patent number: 6232641
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: May 15, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Patent number: 6184083
    Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kiyotaka Miyano, Yukihiro Ushiku
  • Patent number: 6146938
    Abstract: A native film formed on the surface of a silicon substrate is removed. Arsenic is doped into the surface of the silicon substrate to form an n-type impurity diffusion layer as a lower capacitor electrode. A silicon nitride film as a capacitor insulating film is formed on the n-type impurity diffusion layer without growing any oxide film on the surface of the n-type impurity diffusion layer. An upper capacitor electrode is formed on the silicon nitride film.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshitaka Tsunashima, Tsutomu Sato
  • Patent number: 6133121
    Abstract: A plurality of rods are arranged between first and second plates. A plurality of support members formed of heat-resistant strings, for example, SiC are stretched between the rods and wafers are supported by the support members. The wafers are separated from the rods while they are supported on the support members.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: October 17, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura, Shigeru Yonemoto
  • Patent number: 6100132
    Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: August 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Junichiro Iba
  • Patent number: 6093243
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6091117
    Abstract: A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 6087719
    Abstract: A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A photodetector detects the laser beam output from the stacked chips through the alignment holes in these chips. The positions of the chips are so controlled that the amount of the light detected by this photodetector is a maximum.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: July 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshitaka Tsunashima
  • Patent number: 6066872
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5970352
    Abstract: A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: October 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5888876
    Abstract: A method of filling one or more trenches formed in a silicon substrate includes the steps of forming a thin polycrystalline silicon film in a trench such that the thin polycrystalline silicon film is sufficiently thin so as to not close the trench; forming an amorphous silicon film on thin polycrystalline film and the surface of the substrate and in the trenches; and annealing the amorphous silicon film such that the amorphous silicon layer migrates to fill the trenches to a first level. The deposition and annealing steps are performed in ambient atmospheres having low partial pressures of H.sub.2 O and O.sub.2, the annealing temperature is higher than the deposition temperature, and the annealing pressure is greater than the deposition pressure.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5879447
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5849089
    Abstract: Inside a first cylinder for structuring an evaporator, a second cylinder is provided. The second cylinder has an undulated surface and a plurality of fine holes are provided on this surface. A liquid TEOS is contained in a first space positioned between the first cylinder and the second cylinder, and a second space positioned inside the second cylinder is filled with a gas TEOS evaporated from the fine holes. The pressure of the gas TEOS is set to be almost equal to the pressure of the liquid TEOS.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: December 15, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5766785
    Abstract: To react the surfaces of a plurality of semiconductor substrates to be treated to reducing gas in a treating chamber, their corresponding members having surfaces opposite to those surfaces of the substrates on which semiconductor devices are to be manufactured, are arranged. The amount of reducing agent supplied to the surfaces of the substrates is controlled by controlling the reaction of the surfaces of the members to the reducing gas, and the progress of the reducing reaction to each of the substrates is controlled accordingly.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: June 16, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Mikata, Takashi Nakao, Yoshitaka Tsunashima
  • Patent number: 5605574
    Abstract: The wafer support apparatus and method provide a plurality of elastic supports having a smooth curvature for contacting a wafer at a respective plurality of support points. Each elastic support directly contacts the wafer at a support point and expands and/or compresses independently of the other elastic supports to accommodate the bending of the wafer during processing.A wafer support apparatus includes a plurality of flexible elastic supports onto which a wafer is directly positioned, wherein each of the plurality of elastic supports holds the wafer during processing by compressing or expanding in response to bending of the wafer during processing to provide continuous even support for the wafer during processing.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: February 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Katsuya Okumura
  • Patent number: 5582640
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5485034
    Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: January 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Hiroshi Gojohbori, Yoshitaka Tsunashima
  • Patent number: 5451809
    Abstract: A semiconductor device has a substrate and a trench formed therein, the semiconductor device including a dielectric formed on the surface of the trench, a first amorphus silicon film formed on the dielectric film, a dopant film, a second amorphus silicon film, and a capping film formed between the dopant film and one of the first and second amorphus silicon films, the dopant film being formed between the other of the first and second amorphus silicon films and the capping film. The capping film is formed from one of silicon oxide and silicon nitride.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: September 19, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Shiozawa, Yoshitaka Tsunashima