Abstract: A semiconductor device including photosensor capable of imaging with high resolution is disclosed. The semiconductor device includes the photosensor having a photodiode, a first transistor, and a second transistor. The photodiode generates an electric signal in accordance with the intensity of light. The first transistor stores charge in a gate thereof and converts the stored charge into an output signal. The second transistor transfers the electric signal generated by the photodiode to the gate of the first transistor and holds the charge stored in the gate of the first transistor. The first transistor has a back gate and the threshold voltage thereof is changed by changing the potential of the back gate.

Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.

Abstract: An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.

Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.

Abstract: An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

Abstract: A display device that is suitable for increasing its size is provided.

Abstract: A semiconductor device capable of efficiently recognizing images utilizing a neural network is provided. The semiconductor device includes a shift register group, a D/A converter, and a product-sum operation circuit. The product-sum operation circuit includes an analog memory and stores a parameter of a filter. The shift register group captures image data and outputs part of the image data to the D/A converter while shifting the image data. The D/A converter converts the part of the input image data into analog data and outputs the analog data to the product-sum operation circuit.

Abstract: A display device that is driven with low power and a method for operating the display device are provided. The display device includes a host; a controller to which a first signal is supplied from the host; and a display panel to which a second signal is supplied from the controller. When the first signal includes image data, the first signal includes a command indicating the presence of the image data. When the controller detects the command, the controller supplies the image data as the second signal. When the controller does not detect the command, the controller stops supplying the second signal. After the controller stops supplying the second signal for a predetermined time, the controller resumes supplying the second signal regardless of whether or not the first signal includes the command.

Abstract: A display system and vehicle that have novel structures are provided. The display system includes a display panel, a correction circuit, and a memory circuit. The display panel is flexible. The display panel includes a display region and a non-display region. The memory circuit has a function of storing first data about the display region and second data about the non-display region. The non-display region has a region which overlaps with the display region when the display panel is bent. The correction circuit has a function of generating image data to be written to pixels in the display region on the basis of the first data and the second data.

Abstract: A low-power display device in which an operation method is optimized in accordance with the resolution and the frame frequency of a content is provided. The display device includes a display unit and an image receiving apparatus. In the case where the resolution of a content is lower than the resolution that can be displayed by the display device, a source driver and a gate driver included in the display unit output signals to a plurality of source lines and gate lines, and the source driver and the gate driver are operated at lower operation frequencies. Furthermore, the power supply voltages of the logic circuit portions included in the source driver and the gate driver are lowered.

Abstract: Power consumption of a decoder is reduced. The decoder includes an FPGA. The FPGA performs at least one processing to decode the data. In the case where the data has first resolution, an input data signal of the FPGA is a binary signal and a clock frequency of the FPGA is a first frequency. In the case where the resolution of the data is lower than the first resolution, the input data signal of the FPGA is a pulse signal and the FPGA operates at a second frequency which is lower than the first frequency. The FPGA operates at the first clock frequency in the case of decoding 8K data and the FPGA operates at the second clock frequency in the case of decoding 4K or 2K data.

Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.

Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

Abstract: To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring.

Abstract: An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.

Abstract: A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.

Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Abstract: An object is to provide an imaging device in which a circuit for reading a signal is provided in a pixel region. The imaging device includes a first pixel and a second pixel. The first pixel is capable of outputting a first signal output from a pixel circuit included in the first pixel or a second signal input from the first pixel in the previous stage, to the first pixel or the second pixel in the next stage. The second pixel is capable of outputting, to the outside, the first signal or the second signal, which is input from the first pixel in the previous stage, or a third signal output from a pixel circuit included in the second pixel.