Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

Abstract: Power consumption of an interface circuit is to be reduced. A semiconductor device includes a processor and the interface circuit including a register that stores setting information. The register includes a first memory circuit capable of storing the setting information when power supply voltage is supplied, and a second memory capable of storing the setting information when supply of the power supply voltage is stopped. The interface circuit changes a state between a first state, a second state, a third state, and a fourth state. In the first state, the setting information is stored in the first memory. In the second state, the interface circuit operates on the basis of the setting information stored in the first memory circuit. In the third state, the setting information stored in the first memory circuit is stored in the second memory circuit and the supply of the power supply voltage is stopped.

Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.

Abstract: An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

Abstract: A method for transmitting image data to a display device at high speed is provided. Image data to be transmitted is input to a phase modulation portion, and is mixed with a high-frequency carrier wave. The carrier wave is modulated with a technique of phase-shift keying, and output to a transmission line determined in consideration of the transmission characteristics of the high-frequency wave. A phase regulating portion of the phase modulation portion has a function of adjusting the amount of change in phase with the use of an electric signal. A phase demodulation portion beyond the transmission line demodulates the modulated carrier wave and extracts the image data. The multi-bit image data can be transmitted by the technique of the phase-shift keying. The high-speed transmission enables serial conversion of the original image data and decreases the number of transmission lines.

Abstract: A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.

Abstract: An occupant protection device which can protect an occupant without delay is provided. An image taken by an imaging device is analyzed to judge whether there is an object approaching the subject car. In the case where a collision between the object and the subject car is judged to be inevitable, an airbag device is activated before the collision, whereby the occupant can be protected without delay. By using selenium for a light-receiving element of the imaging device, an accurate image can be obtained even under low illuminance. Imaging in a global shutter system leads to an accurate image with little distortion. This enables more accurate image analysis.

Abstract: A semiconductor device capable of retaining a signal sensed by a sensor element is provided. The semiconductor device includes a sensor element, a first transistor, a second transistor, and a third transistor. One electrode of the sensor element is electrically connected to a first gate. The first gate is electrically connected to one of a source and a drain of the third transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. A semiconductor layer includes a metal oxide.

Abstract: A display device that is suitable for increasing its size is provided.

Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract: A low-power display device in which an operation method is optimized in accordance with the resolution and the frame frequency of a content is provided. The display device includes a display unit and an image receiving apparatus. In the case where the resolution of a content is lower than the resolution that can be displayed by the display device, a source driver and a gate driver included in the display unit output signals to a plurality of source lines and gate lines, and the source driver and the gate driver are operated at lower operation frequencies. Furthermore, the power supply voltages of the logic circuit portions included in the source driver and the gate driver are lowered.

Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

Abstract: An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor.

Abstract: A novel semiconductor device or display system is provided. The display system includes a correction circuit having a function of correcting an image signal by utilizing artificial intelligence. Specifically, learning by an artificial neural network enables the correction circuit to correct an image signal so as to alleviate the image discontinuity. Then, by making an inference (recognition) utilizing the artificial neural network which has finished the learning, the image signal is corrected and compensation for the image discontinuity can be made. In this manner, the junction can be inconspicuous on the displayed image, improving the quality of a high-resolution image.

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

Abstract: A novel semiconductor device is provided. The semiconductor device has a function of changing a pixel selection period in accordance with a distance from a driver circuit. Specifically, when the distance between a first pixel and the driver circuit is longer than the distance between a second pixel and the driver circuit, the pulse width of a selection signal supplied to the first pixel is set larger than the pulse width of a selection signal supplied to the second pixel. Accordingly, writing of image signals to pixels provided far from the driver circuit can be accurately performed while the selection period for pixels provided near the driver circuit is kept short.