Patents by Inventor Yoshiyuki Kurokawa

Yoshiyuki Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10769520
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200266761
    Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: Yuki OKAMOTO, Yoshiyuki KUROKAWA
  • Patent number: 10748479
    Abstract: A novel semiconductor device or a novel display system is provided. A signal generation portion monitors display conditions and controls the potentials output from a power supply circuit, in accordance with the display conditions. Specifically, a controller changes the parameter stored in a memory device when display conditions change. Then, the power supply circuit generates the potentials with the use of the changed parameter. Accordingly, the voltage applied to a light-emitting element can be controlled in accordance with the display conditions, which reduces the power consumption in a display portion.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Energy Laboratories Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10733946
    Abstract: A display device that performs image correction in accordance with external light environment is provided. The display device includes a host device and an optical sensor. In addition, the display device includes a processing circuit. The host device has a function of performing arithmetic processing using a neural network on software and a function of performing supervised learning with the neural network. The processing circuit has a function of performing arithmetic processing using a neural network on hardware. The optical sensor has a function of obtaining illuminance of external light. The obtained illuminance of external light is inputted to the host device, and a luminance and color tone preferred by users are regarded as teacher data, whereby learning is performed on the neural network of the host device. A weight coefficient obtained through the learning is used as a weight coefficient of the neural network of the processing circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200234108
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 23, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200227465
    Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 16, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10699794
    Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Publication number: 20200204755
    Abstract: A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200201603
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Application
    Filed: May 7, 2018
    Publication date: June 25, 2020
    Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA
  • Patent number: 10692869
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Yoshiyuki Kurokawa
  • Publication number: 20200193927
    Abstract: A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.
    Type: Application
    Filed: February 20, 2020
    Publication date: June 18, 2020
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Tatsunori INOUE
  • Patent number: 10686080
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 10685992
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20200183483
    Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuki OKAMOTO, Yoshiyuki KUROKAWA
  • Publication number: 20200176493
    Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
    Type: Application
    Filed: May 6, 2018
    Publication date: June 4, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takayuki IKEDA, Yoshiyuki KUROKAWA, Shintaro HARADA, Hidetomo KOBAYASHI, Roh YAMAMOTO, Kiyotaka KIMURA, Takashi NAKAGAWA, Yusuke NEGORO
  • Publication number: 20200176069
    Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Patent number: 10674168
    Abstract: A semiconductor device with a novel structure is provided. Input neuron circuits, hidden neuron circuits, and output neuron circuits are hierarchically connected to one another through plural synapse circuits. Each synapse circuit includes an analog memory which stores data corresponding to a connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit which changes the data in the analog memory, and a weighting circuit which outputs an output signal obtained by weighting an input signal in accordance with data in the analog memory. The analog memory is formed using a transistor including an oxide semiconductor having extremely low off-state current. It is not necessary to mount a large-scale capacitor for holding data and to recover analog data by regular refresh operation; thus, reduction in a chip area and reduction in power consumption are possible.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10672771
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
  • Patent number: 10664748
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200160158
    Abstract: A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.
    Type: Application
    Filed: April 2, 2018
    Publication date: May 21, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki OKAMOTO, Munehiro KOZUMA, Yoshiyuki KUROKAWA, Takayuki IKEDA