Abstract: A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.

Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.

Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

Abstract: Power consumption of an interface circuit is to be reduced. A semiconductor device includes a processor and the interface circuit including a register that stores setting information. The register includes a first memory circuit capable of storing the setting information when power supply voltage is supplied, and a second memory capable of storing the setting information when supply of the power supply voltage is stopped. The interface circuit changes a state between a first state, a second state, a third state, and a fourth state. In the first state, the setting information is stored in the first memory. In the second state, the interface circuit operates on the basis of the setting information stored in the first memory circuit. In the third state, the setting information stored in the first memory circuit is stored in the second memory circuit and the supply of the power supply voltage is stopped.

Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.

Abstract: A semiconductor device including photosensor capable of imaging with high resolution is disclosed. The semiconductor device includes the photosensor having a photodiode, a first transistor, and a second transistor. The photodiode generates an electric signal in accordance with the intensity of light. The first transistor stores charge in a gate thereof and converts the stored charge into an output signal. The second transistor transfers the electric signal generated by the photodiode to the gate of the first transistor and holds the charge stored in the gate of the first transistor. The first transistor has a back gate and the threshold voltage thereof is changed by changing the potential of the back gate.

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Abstract: A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data.

Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided. The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.

Abstract: A memory device with excellent writing performance and excellent storing performance is provided. In the memory device, a first layer overlaps with a second layer. The first layer includes a first transistor including an oxide semiconductor as an active layer. The second layer includes a second transistor and a third transistor each including an oxide semiconductor as an active layer. The off-state current of a transistor formed in the first layer is lower than the off-state current of each of a transistor formed in the second layer. The field-effect mobility of the transistor formed in the second layer is higher than the field-effect mobility of the transistor formed in the first layer.

Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.

Abstract: To achieve high processing capability, a semiconductor device includes first and second circuits, first to third wirings, and first to fourth transistors. The first circuit is electrically connected to the first wiring and a gate of the first transistor. One of a source and a drain of the first transistor is electrically connected to the second wiring. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. The second circuit is electrically connected to the first wiring and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to the third wiring. The other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the second transistor.

Abstract: A display system and vehicle that have novel structures are provided. The display system includes a display panel, a correction circuit, and a memory circuit. The display panel is flexible. The display panel includes a display region and a non-display region. The memory circuit has a function of storing first data about the display region and second data about the non-display region. The non-display region has a region which overlaps with the display region when the display panel is bent. The correction circuit has a function of generating image data to be written to pixels in the display region on the basis of the first data and the second data.

Abstract: To provide an electronic device with reduced power consumption. In the case where rewriting of image data is not performed in an electronic device including a display device, a source driver, a gate driver, an image processing circuit, and the like that drive the display device are power-gated, reducing the power consumption of the electronic device. When power gating is performed, setting data needs to be saved into a memory device in advance. It is preferable that the saving of setting data be performed according to a prediction that power gating is to be performed. To predict whether to perform power gating, learning and calculation using a neural network are carried out. Predictive information about whether to perform power gating is obtained by the calculation, and when power gating is performed, saving of setting data into the memory device is speculatively executed.

Abstract: A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.

Abstract: A novel semiconductor device or display system is provided. The display system includes a correction circuit having a function of correcting an image signal by utilizing artificial intelligence. Specifically, learning by an artificial neural network enables the correction circuit to correct an image signal so as to alleviate the image discontinuity. Then, by making an inference (recognition) utilizing the artificial neural network which has finished the learning, the image signal is corrected and compensation for the image discontinuity can be made. In this manner, the junction can be inconspicuous on the displayed image, improving the quality of a high-resolution image.

Abstract: An electronic device that efficiently compresses a large volume of data included in a broadcast signal and stores the compressed data is to be provided. The broadcast signal is decoded and decompressed through a tuner and a set top box (STB), and a signal (image data) that is decoded and decompressed is inputted to a video display device, so that an image based on the signal is displayed. As a unit for efficiently compressing and storing the image, an electronic device including an encoder, a decoder, and a memory device is used. An image data outputted from the tuner and the STB is compressed using the encoder, and the compressed data is stored in the memory device. To reproduce and display the image data. the compressed image data is decompressed by the decoder, and the decompressed image data is inputted to the video display device.

Abstract: A semiconductor device and electronic device with reduced power consumption are provided. The semiconductor device includes an encoder, a decoder, and a source driver circuit. An output terminal of the encoder is electrically connected to an input terminal of the source driver circuit, and an output terminal of the source driver circuit is electrically connected to an input terminal of the decoder. The encoder converts input image data into feature-extracted image data, and the decoder restores the feature-extracted image data to the original image data. In addition, provision of a circuit that performs convolution processing using a weight filter for the encoder enables calculation using a convolutional neural network.

Abstract: A semiconductor device with a novel structure is provided. Input neuron circuits, hidden neuron circuits, and output neuron circuits are hierarchically connected to one another through plural synapse circuits. Each synapse circuit includes an analog memory which stores data corresponding to a connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit which changes the data in the analog memory, and a weighting circuit which outputs an output signal obtained by weighting an input signal in accordance with data in the analog memory. The analog memory is formed using a transistor including an oxide semiconductor having extremely low off-state current. It is not necessary to mount a large-scale capacitor for holding data and to recover analog data by regular refresh operation; thus, reduction in a chip area and reduction in power consumption are possible.

Abstract: A novel semiconductor device or a novel display system is provided. A signal generation portion monitors display conditions and controls the potentials output from a power supply circuit, in accordance with the display conditions. Specifically, a controller changes the parameter stored in a memory device when display conditions change. Then, the power supply circuit generates the potentials with the use of the changed parameter. Accordingly, the voltage applied to a light-emitting element can be controlled in accordance with the display conditions, which reduces the power consumption in a display portion.