Abstract: A bisphosphite compound of the following formula (A): ##STR1## wherein --Ar--Ar-- is a bisarylene group represented by any one of the formulae (A-I) to (A-III) defined in the specification, and each of Z.sub.1 to Z.sub.4 is a C.sub.4-20 aromatic or heteroaromatic group which may have a substituent, wherein each of substituents on carbon atoms of an aromatic ring adjacent to the carbon atom bonded to the oxygen atom in each of Z.sub.1 to Z.sub.4, is a C.sub.0-2 group, and each pair of Z.sub.1 and Z.sub.2, and Z.sub.3 and Z.sub.4, are not bonded to each other.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A nonvolatile semiconductor memory device using a NAND-type EEPROM includes a memory unit, a management unit, an erasure unit, and a control unit. The memory unit has a memory cell array divided into blocks each constituting a minimum quantity of data that may be erased. The management unit manages unused blocks. The erasure unit discriminates a erased blocks of the unused blocks from a non-erased blocks of the unused blocks to erase data stored in the non-erased blocks. The control unit writes data into at least one block of the unused blocks managed by the management unit. In the control unit, when a content of the written data is obtained by changing data recorded in a different block of the memory unit, and the data recorded in the different block is not necessary, the management unit receives information that the different block is an unused block.

Abstract: A camera includes a feeder for feeding a film having magnetic recording portions, a reader for magnetically scanning magnetic recording portions to generate scan signals, and a judger for judging whether or not a magnetic recording portion has been recorded with magnetic data by comparing scan signals with a threshold value, and a warning device for generating a warning when judgment of the judger is impossible. This apparatus can ensure more accurate judgment as to whether a signal picked up from each recording portion is a magnetic signal.

Abstract: A joint section is provided which connects a flat cable having a plurality of conductive lines with a plurality of lead wires to a plurality of joint terminals. A first end of each of the joint terminals is formed in compliance with a pitch between the two adjacent conductive lines and the second end of the joint terminals is formed in compliance with a pitch between two adjacent lead wires. Each conductive line is held between the first end of the corresponding one of the joint terminals and an auxiliary terminal placed on the conductive line and connected by a welding operation. The second end of the joint terminal is connected with a conductor of the corresponding one of the lead wires.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A camera includes a feeder for feeding a film having magnetic recording portions, a reader for magnetically scanning magnetic recording portions to generate scan signals, and a judger for judging whether or not a magnetic recording portion has been recorded with magnetic data by comparing scan signals with a threshold value, and a warning device for generating a warning when judgment of the judger is impossible. This apparatus can ensure more accurate judgment as to whether a signal picked up from each recording portion is a magnetic signal.

Abstract: Disclosed is a laminate comprising a thermosetting resin-impregnated prepreg layer (A) constituting a surface layer, a rubber or thermoplastic resin layer (B) having a flexibility and a hot melt resin adhesive layer (C), the thermosetting resin-impregnated prepreg layer and rubber or thermoplastic resin layer being heat bonded through the hot melt resin adhesive layer. The layer (A) is a prepreg impregnated with a thermosetting resin selected from a diallyl phthalate resin, an unsaturated polyester, a phenol resin, an aminoalkyd resin, an epoxy resin, an acrylurethane resin and a melamine resin. The rubber or resin of the layer (B) is a rubber or a thermoplastic resin selected from chlorinated polyethylene, polybutene, ethylene-vinyl acetate copolymer, an ethylene-propylene-diene copolymer, a chloroprene polymer, chlorosulfonated polyethylene, a styrene-butadiene copolymer and polyvinyl chloride. In addition, the hot melt resin of the layer (C) is a hot melt resin having a melting point of 60.degree. to 165.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Abstract: A cover plate for covering exposed conductive wires of a flat cable is attached to a surface of an attaching plate for holding the flat cable, and insert molding is performed in such a manner that the cover plate is included. Therefore, direct contact of a portion of flows of synthetic resin for use in performing insert molding that flows along a surface of the attaching plate for holding the flat cable with conductive wires of the flat cable can be prevented. Moreover, if the synthetic resin introduced into another surface of the attaching plate for holding the electric wires flows in joint portions between the conductive wires, the conduction wires of the flat cable are pushed against the cover plate due to the flow of the synthetic resin so that the conductive wires of the flat cable are supported. Thus, the conductive wires of the flat cable can be protected from excess stress when the insert molding operation is performed. Thus, breakage of the conductive wires of the flat cable can be prevented.

Abstract: A NAND-cell type EEPROM having an array of memory cells connected to bit lines. Each cell includes one transistor with floating and control gate electrodes. Electrons are tunneled to or from the floating gate to write data. A sense/latch circuit is connected to the bit lines for selectively performing sense and latch operations of the write data. A program controller is provided for writing and verifying the data into a selected memory cell. Data is rewritten if a resultant threshold voltage in the selected memory cell of the written data is insufficient. A rewrite-data setting section is provided for performing a logic operation with respect to data read from the selected cell and write data being latched into the sense/latch circuit, and for automatically updating a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the memory being verified.

Abstract: In a connector for electric wires (5) and a flat cable (6) in which said electric wires (5) and said flat cable (6) which have exposed conductor portions (5A, 6A) formed at distal ends of said electric wires (5) and said flat cable (6) are held along a plate surface of an attaching plate (21). The exposed conductor portions (5A, 6A) are welded to each other. Insert molding is performed using a synthetic resin material (70) such that at least one portion of said attaching plate (21) and a welded portion between the exposed conductor portions (5A, 6A) are covered, a window portion (25) is formed in said attaching plate (21), and a plurality of bus bars (30) whose front and rear surfaces are exposed to said window portion (25) are arranged at a pitch corresponding to a conductor pitch of said flat cable (6). The exposed conductor portions (6A) of said flat cable (6) and the exposed conductor portions (5A) of said electric wires (5) are sequentially stacked on each other on one surface of each bus bar (30).

Abstract: A joint structure of a flat cable and joint terminals includes a flat cable, a plurality of joint terminals, a terminal holder and a bus bar holder. The flat cable has a plurality of conductors at its front and an insulating coating layer at its rear. The plurality of joint terminals have terminal plates at their first ends and the terminal plates are arranged in conformity with an arrangement pitch of the conductors. The terminal holder includes a first terminal resin layer and holding the joint terminals in such a manner that the first ends of the terminal plates are secured by the first terminal resin layer. The bus bar holder including a first bus bar resin layer and holds a plurality of bus bars whose first ends are arranged in conformity with the arrangement pitch of the conductors in such a manner that the first ends of the bus bars are secured by the first bus bar resin layer. The conductors are sandwiched by and welded to the terminal plates and the bus bars held by the bus bar holder.

Abstract: A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter.

Abstract: A connecting structure for completing an electrical connection between a flat cable and bus bars is provided. The flat cable is provided at an end portion thereof with an exposed conductive part and an ear part arranged on a tip of the flat cable. By bending the exposed conductive part in a direction perpendicular to the plane of the flat cable, the ear part is arranged perpendicular to an extending direction of the flat cable. The bus-bar unit has first and second setting surfaces, a plurality of exposed parts of the bus bars arranged on the first setting surface and an ear holding part arranged on the second setting surface. In the arrangement, the ear part of the flat cable is attached to the ear holding part while the exposed conductive part of the cable is attached to the first setting surface.

Abstract: A method of protecting a conductive connecting part of a flat cable and a protecting structure of the cable are provided. The method includes a step of connecting conductors of the flat cable to conductors of relay wires at the conductive connecting part, a step of arranging a protective member at the exterior of an insulating cover part of the flat cable, a step of interposing the protective member between opposing molding dies and accommodating the conductive connecting part of the flat cable in a cavity defined by the molding dies in a leak-tight manner, and a step of supplying insulating material in the cavity for an insert molding. The protecting structure includes the conductive connecting part, the protective member and the insulating member for enclosing the conductive connecting part together with a leading end of the protective member. The insulating member is formed by insert molding.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A NAND type EEPROM includes block selecting circuits (BSC1 to BSC6) configured to keep a defective block non-selected in the mode for simultaneous writing and simultaneous erasure of all blocks (BLK1-BLK4) to test the device, after the defective block is replaced by a redundant block (SBLK1, SBLK2). This prohibitor a high voltage boosted by a booster circuit for simultaneous writing and simultaneous erasure of all blocks from being applied to the defective block. The block selecting circuits output a "NON-SELECT" signal when a signal instructing simultaneous writing or simultaneous erasure of all blocks is supplied after corresponding fuses (fa-fh)are blown or cut off. Therefore, once a defective block is replaced by a redundant block, there never occurs a voltage drop which may otherwise be caused by leakage of current from the defective block, and the device can be used as a non-defective NAND type EEPROM in all modes including the test mode.

Abstract: A discharge relay electrode is located between terminal electrodes of a gap-type surge absorber. In a microgap embodiment of the invention, a conducting film on a surface of an insulating tube is split by two circumferential gaps spaced apart longitudinally. The discharge relay electrode is positioned between the two gaps. In a gap type surge absorber, the discharge relay electrode is positioned within the insulating tube midway between the end electrodes, substantially filling the cross section of the tube, and dividing the interior of the tube into a plurality of chambers. For both types of surge absorbers, the discharge relay electrode is effective to relay discharge between the terminal electrodes.