Abstract: To weld a flat conductor to another bonding member reliably without leaving a welding scar, a conductive protective member, such as copper plate or the like, with a higher strength than that of a low strength conductive member is placed between the low strength conductive member such as a flat conductor and the horn tip or the anvil to perform welding with the low strength conductive member sandwiched between the protective member and another bonding member such as stranded conductor or the like.

Abstract: A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A nonvolatile semiconductor memory device using a NAND-type EEPROM includes a memory unit, a management unit, an erasure unit, and a control unit. The memory unit has a memory cell array divided into blocks each constituting a minimum quantity of data that may be erased. The management unit manages unused blocks. The erasure unit discriminates erased blocks of the unused blocks from non-erased blocks of the unused blocks to erase data stored in the non-erased blocks. The control unit writes data into at least one block of the unused blocks managed by the management unit. In the control unit, when a content of the written data is obtained by changing data recorded in a different block of the memory unit, and the data recorded on the another block is not necessary, the management unit receives information that the different block is an unused block.

Abstract: An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

Abstract: A module construction method in a steel structure building zone, including steps of: erecting truss column assemblies (1A), (1B) formed by arranging and joining a plurality of pillars; installing a truss beam assembly (1C) between the tops of the two truss column assemblies (1A), (1B) erected in parallel to construct a gate-shaped truss assembly (1D); installing the gate-shaped truss assemblies (1D) in opposition to fit in with the shape of the steel structure; and installing modules (6A), (6B), (6C) . . .

Abstract: A surge detecting element which is connected to surge invading lines and is composed of a gap type discharge tube and a nonlinear resistor both connected in series with each other and one or more of surge absorbing elements each having an impulse discharge starting voltage higher than an impulse discharge starting voltage of the surge detecting element. A light receiving element is provided for the gap type discharge tube in light receiving relationship therewith for detecting a discharge light thereof, a counter circuit for counting a detected signal from the light receiving element is also provided.

Abstract: A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto.

Abstract: A gap-type surge absorbing element and a varistor are assembled end to end in an insulating tube to form a compact surge absorber. Electrodes on the two devices contact a intermediate element to provide electrical connection therebetween. End electrodes seal the insulating tube and provide external connection to the outboard ends of the two devices, thereby putting them in series. The interior of the insulating tube is filled with an inert gas. Embodiments are described using microgap-type and gap-type surge absorbing elements.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A surge absorber 20 is produced by sealing a glass tube 10 by sealing electrodes 11 and 12 in state that the glass tube 10 is incorporated with a surge absorbing element 13 and with inert gas 14. The sealing electrode is constructed of an electrode member 11a made of alloy containing iron and nickel, and a copper thin film 11b or 21b of a predetermined thickness formed on both surfaces of this electrode member or only on one-side surface in contact with the glass tube and facing on an inside of the glass tube. A Cu.sub.2 O film 11c may preferably be formed on a surface of the copper thin film. This sealing electrode can be sealed in an inert gas atmosphere and has a satisfactory sealability to the glass tube with an electron emission accelerating action. In case where the copper thin film is formed on both surfaces of the electrode member, a lead wire can easily be soldered on an outer surface of the sealing electrode.

Abstract: A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range.

Abstract: A discharge relay electrode is located between terminal electrodes of a gap-type surge absorber. In a microgap embodiment of the invention, a conducting film on a surface of an insulating tube is split by two circumferential gaps spaced apart longitudinally. The discharge relay electrode is positioned between the two gaps. In a gap type surge absorber, the discharge relay electrode is positioned within the insulating tube midway between the end electrodes, substantially filling the cross section of the tube, and dividing the interior of the tube into a plurality of chambers. For both types of surge absorbers, the discharge relay electrode is effective to relay discharge between the terminal electrodes.

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range.

Abstract: A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

Abstract: A nonvolatile semiconductor memory device including a memory means having a plurality of storage areas divided in a capacity serving as a management unit, a first managing means for, when data is to be written in the storage areas, circularly arranging the plurality of storage areas such that the plurality of storage areas physically or logically arranged, and managing the storage areas such that the plurality of storage areas are used in accordance with an order of an arrangement of the plurality of storage areas, a second managing means for managing whether data recorded in the plurality of storage areas is changed after a predetermined timing, and a control means for, when data is written in the storage area and a predetermined condition is satisfied, selecting a storage area having data which is not changed after a timing when the second managing means is initialized, moving the data in the selected storage area to another storage area, and initializing the second managing means when data in all the stora

Abstract: A junction box for the protection of electronic devices and communication lines from lightning surges, overcurrent and overvoltage. The box includes sockets for connection to the devices and liens along with a plurality of combinations of surge absorbing elements and low melting point metal wires for the protection feature.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.