Patents by Inventor Young Bae Kim

Young Bae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10777551
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 15, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Publication number: 20200266224
    Abstract: An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventor: Young Bae KIM
  • Publication number: 20200227650
    Abstract: The present invention relates to a novel compound and an organic electroluminescent device including the same, and by using the compound according to the present invention in an organic material layer of an organic electroluminescent device, preferably a light emitting layer, luminous efficiency, driving voltage, lifetime and the like of the organic electroluminescent device may be enhanced.
    Type: Application
    Filed: May 2, 2018
    Publication date: July 16, 2020
    Applicant: DOOSAN CORPORATION
    Inventors: Hong Suk KIM, Young Bae KIM
  • Patent number: 10665625
    Abstract: An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young Bae Kim
  • Publication number: 20200152886
    Abstract: The present disclosure provides an organic electroluminescent device including: an anode; a cathode; and one or more organic material layers interposed between the anode and cathode and selected from the group consisting of a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer, and further including a lifetime enhancement layer (LEL) between the light emitting layer and the electron transporting layer.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Applicant: DOOSAN CORPORATION
    Inventors: Tae Hyung KIM, HoCheol PARK, Young Bae KIM, Chang Jun LEE, Eunjung LEE, Youngmi BEAK
  • Publication number: 20200144511
    Abstract: The present invention relates to a novel compound and an organic electroluminescent device including the same, and by using the compound according to the present invention in an organic material layer, preferably a light emitting layer, of an organic electroluminescent device, luminous efficiency, driving voltage, lifetime and the like of the organic electroluminescent device may be enhanced.
    Type: Application
    Filed: May 2, 2018
    Publication date: May 7, 2020
    Applicant: DOOSAN CORPORATION
    Inventors: Hyung Chan BAE, Young Bae KIM, Ho Jun SON
  • Publication number: 20200126899
    Abstract: A printed circuit board is provided that includes a base substrate including a pair of first edges extending in a first direction and a pair of second edges extending in a second direction, perpendicular to the first direction. A circuit region including a plurality of circuit patterns is disposed on at least one of a first surface and a second surface of the base substrate. A dummy region including a conductive dummy pattern is disposed on at least one of the first surface and the second surface. The conductive dummy pattern is separated from a boundary of the dummy region, and a maximum length of the conductive dummy pattern in the first or second direction passes through a center of the conductive dummy pattern.
    Type: Application
    Filed: April 24, 2019
    Publication date: April 23, 2020
    Inventors: SHLE GE LEE, YOUNG BAE KIM
  • Publication number: 20200118998
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae KIM, Kwang II KIM, Jun Hyun KIM, In Sik JUNG, Jae Hyung JANG, Jin Yeong SON
  • Patent number: 10600907
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 24, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae Kim
  • Patent number: 10573822
    Abstract: The present disclosure provides an organic electroluminescent device including: an anode; a cathode; and one or more organic material layers interposed between the anode and cathode and selected from the group consisting of a hole injection layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injection layer, and further including a lifetime enhancement layer (LEL) between the light emitting layer and the electron transporting layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 25, 2020
    Assignee: DOOSAN CORPORATION
    Inventors: Tae Hyung Kim, HoCheol Park, Young Bae Kim, Chang Jun Lee, Eunjung Lee, Youngmi Beak
  • Patent number: 10573645
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 25, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Publication number: 20200043801
    Abstract: Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 6, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae KIM, Kwang Il KIM
  • Publication number: 20200043837
    Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip arranged on the first substrate, a first group of at least one solder ball arranged on a side surface of the first semiconductor chip, an interposer arranged on the first semiconductor chip and the first substrate and being in contact with the first group of at least one solder ball, and an adhesive layer arranged between the first semiconductor chip and the interposer and configured to expose at least a portion of un upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first group of at least one solder ball.
    Type: Application
    Filed: April 23, 2019
    Publication date: February 6, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shle Ge LEE, Young Bae KIM
  • Publication number: 20200020613
    Abstract: A semiconductor package includes a package substrate, a flip chip coupled to the package substrate, an interposer stacked on the flip chip and including a first terminal and a second terminal at an upper surface thereof, a bonding wire which connects the first terminal and the package substrate and a mold layer which covers the interposer, the flip chip and the bonding wire. The mold layer has a signal hole which exposes the second terminal, and at least one dummy hole spaced apart from the signal hole on an upper surface of the interposer.
    Type: Application
    Filed: January 24, 2019
    Publication date: January 16, 2020
    Inventor: YOUNG BAE KIM
  • Publication number: 20200013889
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae KIM
  • Publication number: 20190367477
    Abstract: The present invention relates to a novel compound having excellent functions, such as electron injection and transport and light emission functions, and an organic electroluminescence device. By using the novel compound in an organic material layer of the organic electroluminescence device, properties of the device such a light emitting efficiency, driving voltage, and life can be improved.
    Type: Application
    Filed: November 21, 2017
    Publication date: December 5, 2019
    Applicant: DOOSAN CORPORATION
    Inventors: Hongsuk KIM, Young Bae KIM, Hoe Moon KIM, Ho Jun SON, Hyungchan BAE
  • Patent number: 10497649
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 10490456
    Abstract: Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 26, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim
  • Patent number: 10461181
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: October 29, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae Kim
  • Publication number: 20190311992
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang