Abstract: A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.

Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

Abstract: A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.

Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

Abstract: A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.

Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.

Abstract: A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command io generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.

Abstract: According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.

Abstract: A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.

Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.

Abstract: A semiconductor apparatus includes a first output control unit and a second output control unit. The first output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert input signals and output the non-inverted input signals to a signal transmission line as transmission signal, and the inversion pipes invert input signals and output the inverted input signals to the signal transmission line as the transmission signals. The second output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert the transmission signals and output the non-inverted transmission signals, and the inversion pipes invert the transmission signals and output the inverted transmission signals.

Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

Abstract: A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.