Patents by Inventor Young Jun Ku
Young Jun Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240080228Abstract: A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.Type: ApplicationFiled: April 13, 2023Publication date: March 7, 2024Inventors: Jin Ook JUNG, Jae Woo PARK, Myoung Bo KWAK, Young Min KU, Kyoung Jun ROH, Jung Hwan CHOI
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Patent number: 11783908Abstract: A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.Type: GrantFiled: November 18, 2021Date of Patent: October 10, 2023Assignee: SK hynix Inc.Inventors: Young Jun Park, Young Jun Ku, Sang Sic Yoon
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Patent number: 11646097Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.Type: GrantFiled: December 2, 2021Date of Patent: May 9, 2023Assignee: SK hynix Inc.Inventors: Young Jun Park, Young Jun Ku, In Keun Kim, Sang Sic Yoon
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Publication number: 20230011546Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.Type: ApplicationFiled: December 2, 2021Publication date: January 12, 2023Inventors: Young Jun PARK, Young Jun KU, In Keun KIM, Sang Sic YOON
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Patent number: 11521696Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.Type: GrantFiled: October 22, 2020Date of Patent: December 6, 2022Assignee: SK hynix Inc.Inventors: Young Jun Park, Young Jun Ku, Myeong Jae Park, Ji Hwan Park, Seok Woo Choi
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Publication number: 20220076769Abstract: A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.Type: ApplicationFiled: November 18, 2021Publication date: March 10, 2022Inventors: Young Jun Park, Young Jun Ku, Sang Sic Yoon
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Publication number: 20210295938Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.Type: ApplicationFiled: October 22, 2020Publication date: September 23, 2021Applicant: SK hynix Inc.Inventors: Young Jun PARK, Young Jun KU, Myeong Jae PARK, Ji Hwan PARK, Seok Woo CHOI
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Patent number: 10600493Abstract: A semiconductor device includes a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.Type: GrantFiled: December 5, 2018Date of Patent: March 24, 2020Assignee: SK hynix Inc.Inventor: Young-Jun Ku
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Publication number: 20190371423Abstract: A semiconductor device includes a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.Type: ApplicationFiled: December 5, 2018Publication date: December 5, 2019Inventor: Young-Jun KU
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Patent number: 10198201Abstract: A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.Type: GrantFiled: January 26, 2017Date of Patent: February 5, 2019Assignee: SK hynix Inc.Inventors: Dae Suk Kim, Young Jun Ku
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Patent number: 10049763Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.Type: GrantFiled: May 4, 2016Date of Patent: August 14, 2018Assignee: SK hynix Inc.Inventors: Chang Hyun Lee, Young Jun Ku
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Patent number: 9959184Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.Type: GrantFiled: October 9, 2015Date of Patent: May 1, 2018Assignee: SK hynix Inc.Inventors: Min Su Park, Young Jun Ku
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Publication number: 20180011645Abstract: A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command io generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.Type: ApplicationFiled: January 26, 2017Publication date: January 11, 2018Applicant: SK hynix Inc.Inventors: Dae Suk KIM, Young Jun KU
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Patent number: 9831859Abstract: According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.Type: GrantFiled: February 19, 2016Date of Patent: November 28, 2017Assignee: SK hynix Inc.Inventors: Ji Hwan Kim, Young Jun Ku
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Patent number: 9793896Abstract: A semiconductor device includes: first to Nth input terminals (where N is an integer equal to or greater than 2); and a redundant input terminal. When a Kth input terminal (where K is an integer ranging from 1 to N?1) is defective among the first to Nth input terminals, (K+1)th to Nth input terminals receive signals of Kth to (N?1)th input terminals, respectively, and the redundant input terminal receives a signal of the Nth input terminal.Type: GrantFiled: March 30, 2017Date of Patent: October 17, 2017Assignee: SK Hynix Inc.Inventors: Young-Jun Ku, Dae-Suk Kim, Jang-Ryul Kim, Jong-Chern Lee
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Patent number: 9659627Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.Type: GrantFiled: March 21, 2016Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Min Su Park, Young Jun Ku
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Publication number: 20170111034Abstract: According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals. The buffer circuit may include a second buffer configured to receive the first and second external clock signals and generate a second pre-clock signal based on raising timings of the first and second external clock signals.Type: ApplicationFiled: February 19, 2016Publication date: April 20, 2017Inventors: Ji Hwan KIM, Young Jun KU
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Patent number: 9571081Abstract: A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.Type: GrantFiled: February 27, 2015Date of Patent: February 14, 2017Assignee: SK HYNIX INC.Inventors: Jin Hwan Kim, Young Jun Ku
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Publication number: 20160364309Abstract: An input/output (I/O) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The I/O line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (IOL), and a signal transceiver configured to perform signal transmission/reception between the IOL and a through silicon via (TSV). The I/O line test device may include a latch unit configured to latch output data of the signal transceiver, and a test controller configured to output a control signal for controlling whether the signal transceiver performs a reception operation in response to a write enable signal and a test signal.Type: ApplicationFiled: October 9, 2015Publication date: December 15, 2016Inventors: Min Su PARK, Young Jun KU
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Patent number: 9466336Abstract: A semiconductor apparatus includes a first output control unit and a second output control unit. The first output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert input signals and output the non-inverted input signals to a signal transmission line as transmission signal, and the inversion pipes invert input signals and output the inverted input signals to the signal transmission line as the transmission signals. The second output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert the transmission signals and output the non-inverted transmission signals, and the inversion pipes invert the transmission signals and output the inverted transmission signals.Type: GrantFiled: January 28, 2015Date of Patent: October 11, 2016Assignee: SK HYNIX INC.Inventors: Min Su Park, Young Jun Ku