Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.

Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Abstract: A half bridge circuit driver chip and the protection method thereof are provided. The high side voltage detecting circuit connects to a high side signal output terminal and detects the high side turn-on voltage of the high side transistor, so as to obtain a high side turn-on signal. The low side voltage detection circuit connects to a low side signal output terminal and detects a low side turn-on voltage of a low side transistor, so as to obtain a low side turn on signal. When the high side turn-on signal and the low side turn-on signal are received by a protection circuit, a reset signal is generated. The reset signal is sent to the high side driving circuit for turning off the high side transistor and to the low side driving circuit for turning off the low side transistor.

Abstract: A driver chip includes a high side input terminal, a pulse generator, a level shift, a current detector, a high side output controller, and a high side output terminal. The high side input terminal receives the high side input signal and the pulse generator transfers the high side input signal into the rise pulse signal and the fall pulse signal. The current detector detects the first current and the second current flowing through the level shift, and the high side output controller generates the high side output signal. The high side output terminal controls the switching of the high side transistor by the high side output signal.

Abstract: A hearing aid device comprising: a body, accommodating a circuit unit; a ear mold, capable of being accommodated in ear canal to convey sound; a connecting portion, capable of connecting the body with the ear mold; a wireless transmission unit, electrically coupled with the circuit unit, capable of communicating with at least one wireless device; and a rechargeable battery unit, coupled with the body and provided with a convex structure on a side facing the body.

Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.

Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.

Abstract: A solid-state imaging device includes multiple photoelectric conversion elements arrayed in a pixel array. The solid-state imaging device also includes a color filter layer having multiple color filter segments above the photoelectric conversion elements. Each of the color filter segments is disposed in a respective pixel of the pixel array. The solid-state imaging device further includes an optical waveguide layer over the color filter layer. The optical waveguide layer includes a waveguide partition grid and a waveguide material in the spaces of the waveguide partition grid. The waveguide material has a refractive index that is higher than the refractive index of the waveguide partition grid. The waveguide material provides the same refractive index for each pixel of the pixel array.

Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active area including a channel region sandwiched between two source/drain regions; an insulation region surrounding the active area from a top view; and a dielectric layer disposed over and in contact with an interface between the insulation region and the source/drain regions. A method of manufacturing the same is also disclosed.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A grinding machine includes a slight gyration module for driving a homogeneous container to undergo an X-axial motion and a Y-axial motion within ±1-3 mm distance, a homogeneous-stick rotation module for rotating a homogeneous stick in the homogeneous container so as to generate an eccentric motion between the homogeneous stick and the homogeneous container, and a homogeneous-stick vertical movement module for vertically moving the homogeneous stick with respect to the homogeneous container. When the homogeneous stick is lowered into the homogeneous container by the homogeneous-stick vertical movement module, an eccentric motion with a 1-3 mm radius of gyration can be activated between the homogeneous container and the homogeneous stick so as to carry out the grinding in a tiny slim space between the homogeneous container and the homogeneous stick; such that the grinding efficiency of the grinding machine can be substantially enhanced.