Patents by Inventor Yu-Chun Chen

Yu-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363702
    Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
  • Patent number: 12133020
    Abstract: A method and a system for verifying an image interface, and an image equipment are provided. The system includes a memory, a receiving module, and a transmitting module; the receiving module connected to an image output interface of a device under test (DUT), the transmitting module connected to an image input interface of the DUT. The method includes obtaining at least one predetermined image from the memory, and generating serial data stream according to the at least one predetermined image; controlling the transmitting module to transmit the serial data stream to the image input interface; controlling the receiving module to obtain returned serial data stream from the image output interface; and determining the image interface of the DUT to be normal when the receiving module successfully obtains the returned serial data stream from the image output interface.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: October 29, 2024
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Chia-Chun Chen, Chien-Hao Su, Yu-Shan Lin
  • Publication number: 20240357943
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
    Type: Application
    Filed: June 30, 2024
    Publication date: October 24, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Publication number: 20240342229
    Abstract: The present disclosure relates to an anti-fatigue Lactobacillus composition. The anti-fatigue Lactobacillus composition, which includes at least one of Lactobacillus brevis GKEX, Lactobacillus plantarum GKK1 and Lactobacillus johnsonii GKJ2 as an active ingredient, administered to a healthy subject for a continuous period of time, can significantly improve fatigue-related biochemical indices and prolong aerobic exercise time to exhaustion, and thus can be used as an active ingredient for preparation of various compositions for anti-fatigue and/or improving athletic ability.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, You-Shan TSAI, Tzu-Chun LIN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, Zi-He WU, Yen-Po CHEN
  • Publication number: 20240345398
    Abstract: An optical assembly for head wearable display includes a light redirecting layer, provided in a first optical path between a first light emitter and a first eye of a viewer, the light redirecting layer including a plurality of three dimensional geometric patterns that are cyclically provided on one surface of the light redirecting layer. The light redirecting layer includes a plurality of subunit sections, each of the plurality of subunit sections respectively includes the plurality of three dimensional geometric patterns with different physical dimensions for respectively receiving and redirecting light emission of different wavelengths of a first light signal emitted by the first light emitter toward the first eye of the viewer with different incident angles, the first light signal corresponds to a first pixel of an image. The plurality of three dimensional geometric patterns include pillar like three dimensional nanostructure protruding from a surface of the light redirecting layer.
    Type: Application
    Filed: February 23, 2023
    Publication date: October 17, 2024
    Applicant: HES IP HOLDINGS, LLC
    Inventors: Jiunn-Yiing LAI, Yu-Chieh CHENG, Ken-Yu CHENG, Guo-Hsuan CHEN, Feng-Chun YEH, Tai-Kuo CHEN
  • Publication number: 20240348921
    Abstract: An image processing device is provided. The device includes an electronic image stabilization (EIS) module and an image signal processing (ISP) module. The EIS module is configured to determine EIS information for a video frame based on motion information that corresponds to the video frame, wherein the EIS information is associated with the target region and the margin region of the video frame. The ISP module is configured to generate a processed video frame based on the EIS information by performing an ISP process only on the target region of the video frame and skipping the ISP process on the margin region of the video frame. The EIS module is further configured to generate a stabilized image based on the EIS information and the processed video frame.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 17, 2024
    Inventors: Meng-Hung CHO, Hsiao-Wei CHEN, Shu-Fan WANG, Yu-Chun CHEN, Te-Hao CHANG, Ying-Jui CHEN
  • Patent number: 12118925
    Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: October 15, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Hsien-Chun Wang, Sin-An Lin, Mei-Yi Li, Yu-Hsun Chiu, Ming-Hung Chuang, Yi-Jung Chen
  • Patent number: 12113071
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee, Chih-Ping Chao, Alexander Kalnitsky
  • Publication number: 20240332220
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Hong-Seng Shue, Yao-Chun Chuang, Yu-Tse Su, Chen-Shien Chen, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240332306
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee, Chih-Ping Chao, Alexander Kalnitsky
  • Patent number: 12107482
    Abstract: A voice coil motor assembly including a base, a frame, an elastic sheet, a housing, and a plurality of shock-absorbing components is provided. The frame is disposed on the base. The frame includes a bottom surface, a top surface, a plurality of side walls and a support frame. One side of the elastic sheet is disposed on the top surface of the frame and the other is disposed on the support frame. The housing is disposed above the base to receive the frame and the elastic sheet. The housing includes a housing top wall and a plurality of housing side walls surrounding the housing top wall. The shock-absorbing components are disposed on the frame and are sandwiched between the frame and the housing side walls of the housing, and/or between the support frame and the housing top wall of the housing.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: October 1, 2024
    Assignee: LANTO ELECTRONIC LIMITED
    Inventors: Fu-Yuan Wu, Yu-Cheng Lin, Shang-Yu Hsu, Tao-Chun Chen
  • Publication number: 20240321572
    Abstract: Provided are semiconductor devices and methods for manufacturing semiconductor devices. A method deposits conformal material to form a conformal liner in the trench and modifies the conformal liner such an upper liner portion is modified more than a lower liner portion. The deposition and modifying steps are repeated while a rate of deposition of the conformal material over a non-modified surface of the conformal liner is faster than a rate of deposition of the conformal material over a modified surface of the conformal liner to form a remaining unfilled gap with a V-shape. The method further includes depositing a conformal material in the remaining unfilled gap.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Fong Lin, Yen-Chun Huang, Zhen-Cheng Wu, Chi On Chui, Chih-Tang Peng, Yu Ying Chen
  • Publication number: 20240322827
    Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 26, 2024
    Applicant: Wiwynn Corporation
    Inventors: Wei-Fang Chang, Yu-Chun Chen, Nan-Huan Lin, Chung-Hui Yen, Shi-Rui Chen
  • Publication number: 20240321780
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution structure, and conductive vias. The molded semiconductor device comprises a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input/output region and a sensing region at the first surface. The first redistribution structure is disposed on the first surface of the sensor die, wherein the first redistribution structure covers the input/output region and exposes the sensing region, and the first redistribution structure comprises a conductive layer having a redistribution pattern and a ring structure. The redistribution pattern is electrically connected with the sensor die. The ring structure surrounds the sensing region and is separated from the redistribution pattern, wherein the ring structure is closer to the sensing region than the redistribution pattern.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hao Chang, Po-Chun Lin, Chun-Ti Lu, Zheng-Gang Tsai, Shih-Wei Chen, Chia-Hung Liu, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240321626
    Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 26, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yang Du, Yung-Fong Lin, Tsung-Hsiang Lin, Yu-Chieh Chou, Cheng-Tao Chou, Yi-Chun Lu, Chun-Hsu Chen
  • Patent number: 12100789
    Abstract: A display device, including a circuit substrate, a light-emitting layer, a quarter-wave plate, and a band-pass polarizing layer, is provided. The light-emitting layer is disposed on the circuit substrate and has light-emitting structures, which are electrically connected to the circuit substrate and include first light-emitting structures, which have a first main light-emitting wavelength. The quarter-wave plate is disposed in overlap with the light-emitting structures and is located between the band-pass polarizing layer and the light-emitting layer. The band-pass polarizing layer includes at least one first band-pass polarizing pattern, which have a first absorption axis. The first wavelength range is the first main light-emitting wavelength±10 nm. An average transmittance of the first band-pass polarizing patterns to light with a wavelength outside the first wavelength range and a polarization direction parallel to the first absorption axis is less than 20%.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: September 24, 2024
    Assignee: Coretronic Corporation
    Inventors: Ping-Yen Chen, Wen-Chun Wang, Chung-Yang Fang, Yu-Fan Chen
  • Publication number: 20240312014
    Abstract: In an automated detection system for acute ischemic stroke, a preprocessor performs registration on a whole-brain image and a standard-brain spatial template to extract individual brain region masks from the whole-brain image. A deep learning encoder performs feature extraction on the whole-brain image and the individual brain region masks, thereby converting the whole-brain image into 2D whole-brain slice images. A first processor maps the individual brain masks onto the whole-brain slice images for registration, thereby generating sets of brain region slice images. A second processor computes the stroke-related weight values of the slice images of each of the sets of brain region slice images and sums the weight values to obtain the characteristic value of each brain region. A disparity-aware classifier determines whether any brain region has acute ischemic stroke according to the characteristic value of each brain region.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 19, 2024
    Applicants: National Yang Ming Chiao Tung University, Kaohsiung Chang Gung Memorial Hospital
    Inventors: Yong-Sheng CHEN, Wei-Che Lin, Shih-Yen Lin, Hsiang-Chun Yang, YU-LIN YEH, Evelyne Calista, Pi-Ling Chiang
  • Patent number: 12094938
    Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
  • Publication number: 20240304535
    Abstract: A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 12, 2024
    Inventors: Chen-Shien Chen, Ting Hao Kuo, Hui-Chun Chiang, Yu-Chia Lai
  • Publication number: 20240306078
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; and a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data. When the audio broadcasting device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the audio broadcasting device, the audio broadcasting device utilizes a target control command to instruct the first and second Bluetooth member devices to synchronously reduce their volume to be lower than a predetermined threshold.
    Type: Application
    Filed: May 3, 2024
    Publication date: September 12, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Bi WEI, Yu Hsuan LIU, Chia Chun HUNG