Abstract: An electronic device is provided. The electronic device includes a board, a first latch mechanism, and an expansion card. A controller is disposed on the board. The first latch mechanism is disposed on the board. The first latch mechanism is electrically connected to the controller. The expansion card is plugged in the first latch mechanism and disposed over the board. The expansion card is electrically connected to the controller through the first latch mechanism. The controller determines a connecting condition of the first latch mechanism according to a connecting signal provided by the expansion card.

Abstract: An electronic device is provided. The electronic device includes a board, a first latch mechanism, and an expansion card. A controller is disposed on the board. The first latch mechanism is disposed on the board. The first latch mechanism is electrically connected to the controller. The expansion card is plugged in the first latch mechanism and disposed over the board. The expansion card is electrically connected to the controller through the first latch mechanism. The controller determines a connecting condition of the first latch mechanism according to a connecting signal provided by the expansion card.

Abstract: An electronic image stabilization (EIS) method includes: obtaining video frames derived from an output of an image sensor, wherein each of the video frames has a full field of view (FOV) of the image sensor; obtaining motion information of the video frames; dynamically estimating, by a processing circuit, EIS margins according to FOV variation of a plurality of cropped images within the video frames respectively; and applying stabilization correction to the cropped images according to the motion information and the EIS margins, to generate a plurality of stabilized images.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank and may not contact the blending tank. The slurry blending tool may include a blending pump partially provided within the blending tank and to blend the one or more materials into the slurry. The slurry blending tool may include an outlet pipe connected to the blending pump and to remove the slurry from the blending tank.

Abstract: A white photosensitive resin composition, a white spacer, a light conversion layer, and a light-emitting device are provided. The white photosensitive resin composition includes a polymerizable compound (A), an alkali-soluble resin (B), a photopolymerization initiator (C), a solvent (D), and a white pigment (E). The polymerizable compound (A) includes an ethylenically-unsaturated monomer (A-1) represented by formula (I-1) and a thiol compound (A-2) having two or more thiol groups in one molecule, wherein based on 100 mass % of the polymerizable compound (A), a total content of the ethylenically-unsaturated monomer (A-1) and the thiol compound (A-2) is 10 mass % to 98 mass %.

Abstract: A photosensitive resin composition for a development process, a spacer, a light conversion layer, and a light-emitting device are provided. The photosensitive resin composition includes an alkali-soluble resin (A), an ethylenically-unsaturated monomer (B), a photopolymerization initiator (C), a solvent (D), and a pigment (E). The alkali-soluble resin (A) includes an alkali-soluble resin (A-1), wherein the alkali-soluble resin (A-1) includes a structural unit represented by formula (I-1) and a structural unit represented by formula (I-2). The photopolymerization initiator (C) includes an acylphosphine oxide compound represented by formula (III-1).

Abstract: A resin composition, a light conversion layer and a light emitting device are provided. The resin composition includes a quantum dot (A), an alkali-soluble resin (B), an ethylenically unsaturated monomer (C), a photoinitiator (D), a solvent (E) and a phenyl-based compound (F). The phenyl-based compound (F) includes at least one of a compound represented by following Formula (F-1) and a compound represented by following Formula (F-2). Based on a total usage amount of the resin composition as 100 parts by weight, a usage amount of the phenyl-based compound (F) is 0.05 to 5 parts by weight. In Formula (F-1) and Formula (F-2), the definition of R1, R3, R4, Y, Z, m, n and p are the same as defined in the detailed description.

Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

Abstract: The disclosure provides a method and a projection device for focal length calibration. The projection device includes a distance sensor, a projection lens, and a controller. The method includes: defining, by the distance sensor, a detection area on a projection surface; dividing, by the controller, the detection area into a plurality of reference areas; detecting, by the distance sensor, a reference distance between the projection device and each reference area; finding, by the controller, at least one first area and at least one second area in the reference areas; and performing, by the controller, a focusing operation of the projection lens only based on the reference distance of each second area.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: An electronic device includes a communication port, a display, a processor, and a memory. The processor detects whether an external device plugs into the communication port, displays a user interface on the display when an external device plugs into the communication port, detects whether the user interface receives a predetermined user operation, recommends relevant data linked to the external device according to predetermined rules when the user interface receives the predetermined user operation, and displays the relevant data linked to the external device on the display.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.