Patents by Inventor Yu-Hsiang Lin

Yu-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Publication number: 20220005957
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11217786
    Abstract: An aqueous lithium-ion battery and an electrode used therein are provided, wherein the electrode includes a current collector, a coating layer, and a composite layer. The coating layer is disposed on at least one surface of the current collector, and the coating layer contains an active material. The composite layer is disposed on a surface of the coating layer. The composite layer includes a first film and a second film, wherein the first film is between the second film and the surface of the coating layer, and the water contact angle of the first film is greater than the water contact angle of the second film.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Hung-Chun Wu, Nae-Lih Wu, Che-Wei Chu, Yu-Hsiang Lin, Yu-Hsiu Chang
  • Patent number: 11209919
    Abstract: A knob device is applicable to a touch panel. The touch panel includes a plurality of panel sensors. The knob device includes a knob cover, a sensing pad, a compensation sensor and a switch. The sensing pad is arranged between the knob cover and the touch panel. The switch is configured to selectively connect the sensing pad to the compensation sensor. When a move event of the knob device occurs, the switch is turned on and the sensing pad is electrically connected to the compensate sensor through the switch, such that a feedback loop is generated by the sensing pad, the compensation sensor and the touch panel to change a quantity of electric charge of at least one of the plurality of panel sensors. When a touch and rotation event of the knob device occurs, a location of the sensing pad controls a rotation sensing signal.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 28, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Hsiang Lin, Chun-Jen Su, Wai-Pan Wu, Cheng-Hung Tsai
  • Publication number: 20210399207
    Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.
    Type: Application
    Filed: April 14, 2021
    Publication date: December 23, 2021
    Inventors: Hsing-Hsiang WANG, Yu-Feng YIN, Jiann-Horng LIN, Huan-Just LIN
  • Publication number: 20210395304
    Abstract: The present disclosure provides peptides comprising a motif having four amino acids, wherein each of the amino acids at N-terminus and C-terminus of the sequence independently has a same or different positively charged side chain, and each of the amino acids between the N-terminal and C-terminal of the motif independently has a same or different uncharged side chain. The present disclosure surprisingly found that these peptides have advantageous effects in inhibiting or decreasing collagen breakdown, increasing production of collagen, elastin and/or hyaluronic acid, retarding aging, improving skin and inhibiting inflammation.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 23, 2021
    Inventors: Yung-Hsiang LIN, Yu-Ling WANG
  • Patent number: 11195918
    Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Patent number: 11190217
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Patent number: 11152515
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Patent number: 11146295
    Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yu-Hsiang Lin
  • Publication number: 20210306010
    Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.
    Type: Application
    Filed: April 30, 2020
    Publication date: September 30, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Yu-Hsiang Lin
  • Publication number: 20210296183
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210296182
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 11112576
    Abstract: One embodiment of the invention provides an optical lens including a first lens group with at least two lenses, a second lens group with at least two lenses, and a parting line located between the first lens group and the second lens group. Each of the lenses of the first and the second lens groups is associated with a respective distance, the respective distance is a distance value measured along an optical axis between two focal points of two end points of an image circle diameter formed at an image plane of the optical lens, under the condition that an optical center of one of the lenses is shifted a distance away from the optical axis. The two lenses with the two largest distance values among all lenses are disposed on the same side of the parting line.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 7, 2021
    Assignee: Ray Optics Inc.
    Inventors: Yu-Hsiang Lin, Chen-Cheng Lee, Wei-Chih Hung
  • Patent number: 11096312
    Abstract: A heat dissipation apparatus includes a heat sink unit, a flow guiding structure and a fan. In addition, the heat sink unit includes a base and a fin set arranged on the base. The flow guiding structure includes an air shield and an engagement frame arranged at one end of the air shield. The air shield includes an enclosure space formed at an internal thereof. The enclosure space includes an opening formed at two ends of the air shield respectively, and the air shield covers an exterior of the fin set with the enclosure space. The engagement frame is selectively arranged at an exterior of any one of the openings of the air shield; and a fan is arranged on the engagement frame.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 17, 2021
    Assignee: AIC INC.
    Inventors: Yen-Chih Chen, Chi-Yuan Hsiao, Hsih-Ting You, Yu-Hsiang Lin
  • Patent number: 11062954
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210202308
    Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 1, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210193509
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure dividing the fin-shaped structure into a first portion and a second portion as the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion, a spacer around the top portion, a first epitaxial layer adjacent to one side of the top portion, and a second epitaxial layer adjacent to another side of the top portion.
    Type: Application
    Filed: March 3, 2021
    Publication date: June 24, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210193823
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 24, 2021
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin