Patents by Inventor Yu-Hsiang Lin

Yu-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211915
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20240395909
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20240379451
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20240371855
    Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen
  • Publication number: 20240371703
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20240362174
    Abstract: A driver adaptable to a debugging system includes a driver controller, and a driver general-purpose input and output (GPIO) controlled by the driver controller. The driver GPIO directly transfers a debug log of status messages of a touchscreen to a host general-purpose input and output (GPIO) of a host without handshaking between the driver and the host.
    Type: Application
    Filed: April 29, 2023
    Publication date: October 31, 2024
    Inventors: Yu-Nian Ou, Chun-Kai Chuang, Pei-Yuan Hung, Yu-Hsiang Lin
  • Publication number: 20240355894
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20240347588
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.
    Type: Application
    Filed: May 12, 2023
    Publication date: October 17, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Yu-Hsiang Lin, Po-Kuang Hsieh, Jia-He Lin, Sheng-Yao Huang
  • Publication number: 20240347583
    Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.
    Type: Application
    Filed: May 10, 2023
    Publication date: October 17, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Sheng Yang, Yi-Wen Chen, Hung-Yi Wu, YI CHUEN ENG, Yu-Hsiang Lin
  • Patent number: 12110374
    Abstract: A recyclable crosslinked polymeric foam includes a reaction product of 0.1 to 10 parts by weight of a crosslinking agent and 0.1 to 5 parts by weight of a radical initiator, based on 100 parts by weight of a polymeric material. The crosslinking agent is represented by the following formula: wherein R is an alkylene group having 2 to 10 carbon atoms, an arylene group having 6 to 18 carbon atoms, or a cycloalkylene group having 6 to 18 carbon atoms.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 8, 2024
    Assignee: USI Corporation
    Inventors: Yung-Shen Chang, Chun-Fan Hsieh, Yu-Hsiang Lin
  • Publication number: 20240322036
    Abstract: A semiconductor device includes a substrate, a buried oxide layer in the substrate and near a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure disposed on the gate dielectric layer and overlapping the buried oxide layer, a source region and a drift region in the substrate and respectively at two sides of the gate structure, wherein the drift region partially covers a lower edge of the buried oxide layer and exposes a side edge of the buried oxide layer, and a drain region in the drift region.
    Type: Application
    Filed: June 7, 2024
    Publication date: September 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Publication number: 20240313046
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.
    Type: Application
    Filed: April 13, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Guang-Yu Lo, Chun-Tsen Lu, Chung-Fu Chang, Chih-Shan Wu, Yu-Hsiang Lin, Wei-Hao Chang
  • Patent number: 12094783
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: September 17, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 12094956
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: September 17, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 12074070
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: August 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 12068309
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: August 20, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen
  • Patent number: 12057483
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: August 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20240248560
    Abstract: A touch detection circuitry includes an analog-to-digital converter (ADC), a controller, and a packet generator. The ADC is arranged to convert touch signals of a touch panel from analog form into digital form. The controller is electrically connected to the ADC, and is configured to calculate at least one coordinate point, at least one touch event type, and at least one touch size respectively corresponding to at least one touch event on the touch panel based on the touch signals. The packet generator is electrically connected to the controller, and is configured to encapsulate the at least one coordinate point, the at least one touch event type, and the at least one touch size into a touch data packet.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 25, 2024
    Inventors: Yu Nian OU, Chun Kai CHUANG, Yu-Hsiang LIN, Te Yu HUANG
  • Patent number: 12040396
    Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Zen-Jay Tsai, Yu-Hsiang Lin
  • Publication number: 20240213247
    Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 27, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Yu-Hsiang Lin, Zen-Jay Tsai, Chun-Hsien Lin