Patents by Inventor Yu-Hsien Lin

Yu-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117227
    Abstract: A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.
    Type: Application
    Filed: April 25, 2024
    Publication date: April 10, 2025
    Inventors: Ching-Yeh CHEN, Yi-Wei HO, Te-Hsin LIN, Shih-Ting HUANG, Chung Hao HO, Yu-Hsien LIN, Chiu-Jen LIN, Cheng-Che CHEN
  • Publication number: 20250081512
    Abstract: A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 6, 2025
    Inventors: Ya-Yi Tsai, Chi Yuen Pak, Bo-Hong Chen, Han-Wei Chen, Yu-Hsien Lin
  • Patent number: 12241698
    Abstract: A connecting device includes a floating connector, a case, and an elastic sheet. The floating connector has a channel configured to let a liquid pass through it. The elastic sheet includes a first extending structure, a second extending structure, and a curved structure. The first extending structure is affixed to the case. The second extending structure is connected to the floating connector. The head end and the tail end of the curved structure are respectively connected to the first extending structure and the second extending structure.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 4, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Yu-Hsien Lin
  • Patent number: 12188877
    Abstract: An automated optical double-sided inspection apparatus includes a first image-capturing portion, a second image-capturing portion, a platform, a first light-blocking portion, a second light-blocking portion, and a processing portion. The platform carries an external object. When the processing portion operates in a first capturing mode, the second light-blocking portion blocks visible light from passing therethrough, while the first light-blocking portion allows visible light to pass therethrough, so that the first image-capturing portion shoots a first side of the external object through the first light-blocking portion to obtain a first image.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 7, 2025
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Yee Siang Gan, Sze-Teng Liong, Shih-Kai Fan, Che-Ming Li, Yu-Hsien Lin
  • Publication number: 20240371869
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 12132050
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240332420
    Abstract: A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh CHAO, Ryan Chia-Jen CHEN, Yih-Ann LIN, Yu-Hsien LIN, Li-Wei YIN, Tzu-Wen PAN, Jih-Sheng YANG
  • Publication number: 20240321739
    Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jih-Sheng Yang, Li-Wei Yin, Yu-Hsien Lin, Tzu-Wen Pan, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240313091
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
  • Publication number: 20240274100
    Abstract: A frame rate control method is provided. A primary scenario and a non-primary scenario are identified according to two or more windows displayed on a screen. Each of the primary scenario and the non-primary scenario is performed by an individual application. A frame rate of the non-primary scenario is decreased when a performance index indicates that a first condition is present. The application corresponding to the non-primary scenario is disabled when the performance index indicates that a second condition is present after decreasing the frame rate of the non-primary scenario, so as to remove the window corresponding to the non-primary scenario from the screen.
    Type: Application
    Filed: January 18, 2024
    Publication date: August 15, 2024
    Inventors: Chung-Yang CHEN, Chia-Chun HSU, Jei-Feng LI, Yi-Hsin SHEN, Guo LI, Ta-Chang LIAO, Yu-Chia CHANG, Hung-Hao CHANG, Po-Ting CHEN, Yu-Hsien LIN
  • Publication number: 20240250154
    Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
    Type: Application
    Filed: February 26, 2024
    Publication date: July 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen
  • Patent number: 12027608
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
  • Patent number: 12020987
    Abstract: A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hsien Lin, Chang-Ching Yeh
  • Publication number: 20240121935
    Abstract: Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Y.L. Cheng, Tzu-Wen Pan, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240120388
    Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20240112957
    Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Xuan Wang, Cheng-Chun Tseng, Yi-Chun Chen, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240105795
    Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Ye Liu, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Patent number: 11942532
    Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen