Patents by Inventor Yu-Hsien Lin
Yu-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9804775Abstract: A method for managing user interface of an electronic device includes detecting touch points on a back panel of the electronic device within a predetermined time interval when the electronic device is unlocked. When a first number of the detected touch points on a left part of a back panel is more than a second number of the detected touch points on a right part of the back panel, icons are displayed on a right part of a display device of the electronic device. When a first number of the detected touch points on the left part of the back panel is less than the second number of the detected touch points on the right part of the back panel, the icons are displayed on a left part of the display device.Type: GrantFiled: May 15, 2015Date of Patent: October 31, 2017Assignee: FIH (HONG KONG) LIMITEDInventors: Yu-Hsien Lin, Hung-Ling Wei
-
Publication number: 20170309718Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: ApplicationFiled: July 6, 2017Publication date: October 26, 2017Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
-
Patent number: 9799567Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.Type: GrantFiled: October 23, 2014Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
-
Patent number: 9711604Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: GrantFiled: March 24, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
-
Publication number: 20170194443Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.Type: ApplicationFiled: March 24, 2016Publication date: July 6, 2017Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
-
Publication number: 20170186867Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
-
Patent number: 9595477Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.Type: GrantFiled: January 20, 2011Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
-
Publication number: 20160216613Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
-
Publication number: 20160124631Abstract: A method for managing user interface of an electronic device includes detecting touch points on a back panel of the electronic device within a predetermined time interval when the electronic device is unlocked. When a first number of the detected touch points on a left part of a back panel is more than a second number of the detected touch points on a right part of the back panel, icons are displayed on a right part of a display device of the electronic device. When a first number of the detected touch points on the left part of the back panel is less than the second number of the detected touch points on the right part of the back panel, the icons are displayed on a left part of the display device.Type: ApplicationFiled: May 15, 2015Publication date: May 5, 2016Inventors: YU-HSIEN LIN, HUNG-LING WEI
-
Publication number: 20160118303Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.Type: ApplicationFiled: October 23, 2014Publication date: April 28, 2016Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
-
Patent number: 9304403Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.Type: GrantFiled: January 2, 2013Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
-
Patent number: 9153655Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.Type: GrantFiled: May 20, 2014Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
-
Patent number: 9111906Abstract: The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region.Type: GrantFiled: May 20, 2014Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
-
Patent number: 9082789Abstract: An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.Type: GrantFiled: May 13, 2011Date of Patent: July 14, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hung Huang, Yu-Hsien Lin, Ming-Yi Lin, Jyh-Huei Chen
-
Publication number: 20150097662Abstract: A flexible board type tire pressure sensor device includes a flexible PC board having a first surface bonded to an inside wall of a tire of a vehicle wheel and a second surface opposite to the first surface, a sensor module installed in the second surface of the flexible PC board for sensing a variety of statuses of the vehicle wheel, a transmission terminal set installed in the second surface of the flexible PC board and electrically connected with the sensor module for allowing transmission of a communication program to the sensor module, and an antenna installed in the second surface of the flexible PC board and electrically connected with the sensor module for sending out a sensor signal generated by the sensor module. Thus, the flexible board type tire pressure sensor device has excellent structural stability to provide accurate sensing results.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: CUB ELECPARTS INC.Inventors: SAN-CHUAN YU, TZU-WEN KO, TSAN-NUNG WANG, YEN-HUNG LIN, YU-HSIEN LIN, KUO-TING LEE
-
Publication number: 20140334677Abstract: A multi-computer vision recognition system for a level crossing obstacle is disclosed, comprising vision image systems, a position determination system, an obstacle determination resolution system and a power unit, where vision image systems which may operate all day long operate simultaneously, information of the single vision image systems is each computed by using the position determination system, and then the computed result is introduced to the obstacle determination resolution system for determination, whereby achieving an increased obstacle recognition result and a promoted obstacle recognition accuracy.Type: ApplicationFiled: May 12, 2014Publication date: November 13, 2014Applicant: China Engineering Consultants, Inc.Inventors: Tsai-Wen Kuo, Hsu Ju, Wei-Hua Chieng, Huey-Ming Tseng, Kung-Yu Liu, Hsin-Chu Tsai, Wan-Lee Fu, Ming-Hung Chien, Li-Keng Cheng, Chih-Hui Wen, Yu-Hsien Lin
-
Publication number: 20140291768Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.Type: ApplicationFiled: May 20, 2014Publication date: October 2, 2014Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
-
Publication number: 20140262148Abstract: A clip for fixing a heat sink on a retaining bracket includes an elastic supporter, an operating member, a movable fastener and a fixing bar. Two ends of the elastic supporter have a connecting portion and a first buckle portion, respectively. The operating member has a resisting portion, a pivot portion and an operating bar. The pivot portion pivots to the connecting portion. The movable fastener installs on the resisting portion and the connecting portion, and includes two sliding slots, a resisting surface and a second buckle portion. The resisting portion has an arc surface for resisting against the resisting surface. The distance between the apex of the arc surface and the pivot portion is the largest distance between the arc surface and the pivot portion. When the clip is locked, the junction of the resisting portion and the resisting surface excludes the apex of the arc surface.Type: ApplicationFiled: July 18, 2013Publication date: September 18, 2014Inventors: Yu-Hsien LIN, Li-Kuang TAN
-
Publication number: 20140246728Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.Type: ApplicationFiled: May 20, 2014Publication date: September 4, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang
-
Publication number: 20140248752Abstract: The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region.Type: ApplicationFiled: May 20, 2014Publication date: September 4, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun Jing Lin, Wei-Han Fan, Yu-Hsien Lin, Yimin Huang