Patents by Inventor Yu-Hung Cheng

Yu-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220303904
    Abstract: A method for a UE for performing a dormant operation is provided. The method includes receiving, from a BS, an RRC configuration indicating a set of one or more dormancy cell groups, wherein a group of serving cells belongs to a specific dormancy cell group in the set of one or more dormancy cell groups; receiving, from the BS, a signal including a bitmap, each bit of the bitmap being associated with a respective dormancy cell group in the set of one or more dormancy cell groups; and switching, based on a bit in the bitmap that is associated with the specific dormancy cell group, active BWPs of all serving cells included in the group of serving cells to a dormant BWP or to a non-dormant BWP.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: HSIN-HSI TSAI, CHIA-HUNG WEI, YU-HSIN CHENG, WAN-CHEN LIN, CHIE-MING CHOU
  • Publication number: 20220298634
    Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Yu-Ting TSAI, Chung-Liang CHENG, Wen-Cheng CHENG, Che-Hung LIU, Yu-Cheng SHEN, Chyi-Tsong NI
  • Publication number: 20220293642
    Abstract: In some embodiments, the present disclosure relates to an integrated chip, including a substrate, a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type, and a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and including a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type, a second isolation epitaxial layer arranged along inner sidewalls of the first isolation epitaxial layer and having a second doping type different than the first doping type, and an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer.
    Type: Application
    Filed: June 21, 2021
    Publication date: September 15, 2022
    Inventors: Yu-Hung Cheng, Ching I Li
  • Publication number: 20220283670
    Abstract: A three-dimensional sensing device includes a pressure sensing film, a silver nanowire electrode, a first touch sensing electrode layer, and a second touch sensing electrode layer. The pressure sensing film includes a substrate and a polarized pressure sensing layer. The polarized pressure sensing layer is disposed on and in contact with a first side of the substrate. The silver nanowire electrode is disposed on a side of the polarized pressure sensing layer opposite to the substrate. The first touch sensing electrode layer is disposed on and in contact with a second side of the substrate and includes a patterned electrode with burr etching. The patterned electrode includes first-axis electrodes. A gap between adjacent two first-axis electrodes is between 20 ?m to 35 ?m. The second touch sensing electrode layer is disposed on a side of the first touch sensing electrode layer opposite to the polarized pressure sensing layer.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Inventors: Feng-Ming Lin, Yu-Ting Chan, Lien-Hsin Lee, Tai-Shih Cheng, Ren-Hung Wang
  • Patent number: 11436483
    Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: September 6, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
  • Publication number: 20220264633
    Abstract: A method for uplink transmission performed by a UE is provided. The method includes: receiving a first configured grant configuration that allocates a first PUSCH duration; receiving a second configured grant configuration that allocates a second PUSCH duration, wherein the second PUSCH duration overlaps with the first PUSCH duration; obtaining a first HARQ process ID for the first PUSCH duration, then determining whether a first configured grant timer associated with the first HARQ process ID is running; obtaining a second HARQ process ID for the second PUSCH duration, then determining whether a second configured grant timer associated with the second HARQ process ID is running; and selecting one of the first PUSCH duration and the second PUSCH duration for an uplink transmission based on whether the first configured grant timer is running and whether the second configured grant timer is running.
    Type: Application
    Filed: March 2, 2022
    Publication date: August 18, 2022
    Inventors: HENG-LI CHIN, CHIA-HUNG WEI, WAN-CHEN LIN, YU-HSIN CHENG, CHIE-MING CHOU
  • Publication number: 20220241759
    Abstract: A regeneration method of a nitrogen-containing carbon catalyst includes the following steps: roasting the nitrogen-containing carbon catalyst in a nitrogen-containing atmosphere to obtain a regenerated nitrogen-containing carbon catalyst. The method is a universal method, which is suitable for nitrogen-doped carbon catalysts and can be used to regenerate a nitrogen-containing carbon catalyst for producing vinyl chloride (VC) through 1,2-dichloroethane cracking. The method can greatly reduce the production cost of the catalyst and increase the service life of the catalyst, and a regeneration process thereof is fast, simple, and controllable, and does not require high temperatures.
    Type: Application
    Filed: November 26, 2020
    Publication date: August 4, 2022
    Applicants: DALIAN INSTITUTE OF CHEMICAL PHYSICS, CHINESE ACADEMY OF SCIENCES, FORMOSA PLASTICS CORPORATION
    Inventors: Sisi FAN, Jinming XU, Yanqiang HUANG, Hongmin DUAN, Tao ZHANG, MING-HUNG CHENG, Wan-tun HUNG, Yu-Cheng CHEN, Chien-Hui WU, Ya-Wen CHENG, Ming-Hsien WEN, Chao-Chin CHANG, Tsao-Cheng HUANG, Lu-Chen YEH
  • Patent number: 11404465
    Abstract: Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ru-Liang Lee, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11405868
    Abstract: A method performed by a User Equipment (UE) for power saving operations includes the UE receiving a first Radio Resource Control (RRC) configuration indicating at least one dormancy cell group, receiving a second RRC configuration indicating a first Bandwidth Part (BWP), on which the UE is configured with a dormant operation, for a serving cell, receiving a third RRC configuration indicating a second BWP, on which the UE is not configured with the dormant operation, for the serving cell, receiving a Power Saving Signal (PSS) including a bitmap, determining an active BWP of the serving cell as the first BWP after determining that a bit associated with the dormancy cell group in the bitmap is set to a first value, and determining the active BWP of the serving cell as the second BWP after determining that the bit is set to a second value.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 2, 2022
    Assignee: FG Innovation Company Limited
    Inventors: Hsin-Hsi Tsai, Chia-Hung Wei, Yu-Hsin Cheng, Wan-Chen Lin, Chie-Ming Chou
  • Publication number: 20220139769
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Patent number: 11264469
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Publication number: 20220059364
    Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
  • Publication number: 20220037199
    Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.
    Type: Application
    Filed: April 16, 2021
    Publication date: February 3, 2022
    Inventors: Yu-Hung Cheng, Yu-Chun Chang, Ching I Li, Ru-Liang Lee
  • Patent number: 11232974
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Publication number: 20210391362
    Abstract: Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Ru-Liang LEE, Yu-Hung CHENG, Yeur-Luen TU
  • Patent number: 11171039
    Abstract: A composite semiconductor substrate includes a semiconductor substrate, an oxygen-doped crystalline semiconductor layer and an insulative layer. The oxygen-doped crystalline semiconductor layer is over the semiconductor substrate, and the oxygen-doped crystalline semiconductor layer includes a crystalline semiconductor material and a plurality of oxygen dopants. The insulative layer is over the oxygen-doped crystalline semiconductor layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11171015
    Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
  • Publication number: 20210335861
    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.
    Type: Application
    Filed: September 11, 2020
    Publication date: October 28, 2021
    Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
  • Patent number: 11158534
    Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
  • Publication number: 20210305131
    Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Inventors: Yu-Hung Cheng, Shih-Pei Chou, Yeur-Luen Tu, Alexander Kalnitsky, Tung-I Lin, Wei-Li Chen