Patents by Inventor Yu-Hung Cheng
Yu-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12232309Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.Type: GrantFiled: February 4, 2022Date of Patent: February 18, 2025Assignee: WINBOND ELECTRONICS CORP.Inventors: Yu-Ping Hsiao, Cheol-Soo Park, Chun-Hung Cheng, Wei-Chieh Chuang, Wei-Chao Chou, Yen-Min Juan
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Publication number: 20250056550Abstract: Uplink transmission performed by a UE is provided. The UE receives configured grant (CG) configurations for allocating a group of Physical Uplink Shared Channel (PUSCH) durations in a bandwidth part (BWP), each configured grant configuration having a priority level corresponding to the allocated PUSCH duration, wherein at least two of the PUSCH durations in the group overlap in a time domain; identifies a set of PUSCH durations for transmitting a medium access control (MAC) protocol data unit (PDU) generated from available data from the group of PUSCH durations; selects a PUSCH duration from the identified set of PUSCH durations as a prioritized PUSCH duration based on a comparison of the priority levels corresponding to the identified set of PUSCH durations; and transmits the MAC PDU, via the transceiver, on the prioritized PUSCH duration.Type: ApplicationFiled: August 15, 2024Publication date: February 13, 2025Inventors: Heng-Li Chin, Chia-Hung Wei, Wan-Chen Lin, Yu-Hsin Cheng, Chie-Ming Chou
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Patent number: 12212072Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.Type: GrantFiled: December 19, 2022Date of Patent: January 28, 2025Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventors: Hsin Hung Lin, Yu Shu Tai, Wei Chen Cheng
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Patent number: 12213303Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.Type: GrantFiled: April 21, 2022Date of Patent: January 28, 2025Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
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Patent number: 12205854Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.Type: GrantFiled: September 19, 2023Date of Patent: January 21, 2025Assignee: InnoLux CorporationInventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
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Patent number: 12165911Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.Type: GrantFiled: August 4, 2023Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
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Patent number: 12148756Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: GrantFiled: July 19, 2022Date of Patent: November 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Publication number: 20240379713Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
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Publication number: 20240379684Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
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Publication number: 20240379692Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Yu-Hung Cheng, Ching I Li, Chen-Hao Chiang, Eugene I-Chun Chen, Chin-Chia Kuo
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Publication number: 20240371902Abstract: In some embodiments, the present disclosure relates to an integrated chip, including a substrate, a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type, and a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and including a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type, a second isolation epitaxial layer arranged along inner sidewalls of the first isolation epitaxial layer and having a second doping type different than the first doping type, and an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Inventors: Yu-Hung Cheng, Ching I Li
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Publication number: 20240355855Abstract: The problem of forming a deep trench isolation (DTI) structure suitable for photodetectors having a narrow pitch is solved by a process in which a p-doped epitaxial layer is grown on the sidewalls of trenches formed by etching. The epitaxial layer becomes part of the active region of any adjacent photodetectors and narrows the DTI structure that is formed by dielectric in the trenches. The epitaxial layer may be allowed to close the trench mouths and to grow on the front side. Floating diffusion regions and the like may then be formed directly over the DTI structure. Optionally, dislocations in the epitaxial layer are removed by laser annealing. Optionally the epitaxial layer is planarized after annealing. The trenches may be accessed from the back side by thinning the substrate, whereupon the trenches may be partially or completely filled with dielectric to form the DTI structure.Type: ApplicationFiled: July 18, 2023Publication date: October 24, 2024Inventors: Yu-Hung Cheng, Szu-Yu Wang, Ching I Li
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Publication number: 20240347377Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
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Patent number: 12074036Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.Type: GrantFiled: November 5, 2021Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
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Patent number: 12074186Abstract: In some embodiments, the present disclosure relates to an integrated chip, including a substrate, a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type, and a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and including a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type, a second isolation epitaxial layer arranged along inner sidewalls of the first isolation epitaxial layer and having a second doping type different than the first doping type, and an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer.Type: GrantFiled: June 21, 2021Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Ching I Li
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Publication number: 20240282775Abstract: A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.Type: ApplicationFiled: April 29, 2024Publication date: August 22, 2024Inventors: YU-HUNG CHENG, CHING I LI, CHIA-SHIUNG TSAI
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Patent number: 12040221Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.Type: GrantFiled: January 19, 2022Date of Patent: July 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
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Patent number: 12002813Abstract: A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.Type: GrantFiled: August 30, 2021Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hung Cheng, Ching I Li, Chia-Shiung Tsai
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Publication number: 20240072082Abstract: A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yu-Hung CHENG, Tzu-Jui WANG, Ching I. LI
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Publication number: 20240030222Abstract: An insulator layer of a trap-rich silicon-on-insulator (SOI) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. The silicon layer of the trap-rich SOI wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. The second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. Accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. Thus, operations to form the trap-rich SOI wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich SOI wafer to be formed to a lesser thickness.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Inventors: Yu-Hung CHENG, Ching I LI