Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.

Abstract: A probe card, a method for designing the probe card, a method for producing a tested semiconductor device, a method for testing an unpackaged semiconductor by the probe card, a device under test, and a probe system are provided. The probe card includes a wiring substrate, a connection carrier board, and a probe device. At least two probes form a differential pair electrically connected to a loopback line of the connection carrier board to form a test signal loopback path. The probe device has a probe device impedance on the test signal loopback path. The loopback line has a loopback line impedance on the test signal loopback path. A difference between the probe device impedance on the test signal loopback path and the loopback line impedance on the test signal loopback path is in an impedance range.

Abstract: A boron (B) layer may be formed as a passivation layer in a recess in which a vertical transfer gate is to be formed. The recess may then be filled with a gate electrode of the vertical transfer gate over the passivation layer (and/or one or more intervening layers) to form the vertical transfer gate. The passivation layer may be formed in the recess by epitaxial growth. The use of epitaxy to grow the passivation layer enables precise control over the profile, uniformity, and boron concentration in the passivation layer. Moreover, the use of epitaxy to grow the passivation layer may reduce the diffusion length of the passivation layer into the substrate of the pixel sensor, which provides increased area in the pixel sensor for the photodiode.

Abstract: An insulator layer of a trap-rich silicon-on-insulator (SOI) wafer is formed on a trapping layer over a high-temperature substrate instead of forming the insulator layer on a bulk silicon substrate. The silicon layer of the trap-rich SOI wafer is formed on a second wafer and is bonded to the insulator layer that was grown on the trapping layer. The second wafer is then removed by grinding, polishing, and/or another technique such that no cutting of the silicon device layer is performed, and therefore little to no surface damage is caused to the silicon layer. Accordingly, a high-temperature annealing operation to remove surface damage that would otherwise be caused by cutting of the silicon layer may be omitted. Thus, operations to form the trap-rich SOI wafer may be performed at lower temperatures, which enables the trapping layer of the trap-rich SOI wafer to be formed to a lesser thickness.

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: A cyclic pre-cleaning technique may be used to clean the surfaces of a recess in which a deep trench isolation (DTI) structure is to be formed. The cyclic pre-cleaning technique may include performing one or more deposition and etch cycles to remove oxygen from the surfaces of the recess to reduce the oxygen concentration in the surfaces of the recess. A passivation layer may be formed in the recess after the cyclic pre-cleaning technique is used to clean the surfaces. The cyclic pre-cleaning technique may include the use of germanium (Ge) to bond with oxygen in the surfaces of the recess, which results in the formation of germanium oxide (GeO). The germanium oxide is removed, resulting in reduced oxygen concentration in the surfaces of the recess. The reduced oxygen concentration increases the quality of epitaxial growth of the passivation layer in the recess.

Abstract: A boron layer may be formed as a passivation layer in a recess in which a deep trench isolation structure (DTI) structure is to be formed. The boron layer results in formation of a boron-silicon interface between the DTI structure and a photodiode of a pixel sensor included in a pixel array. The boron-silicon interface functions as a diode junction, which resists penetration of photons into the DTI structure. This reduces and/or minimizes photon transmission through the DTI structure, which reduces and/or minimizes optical crosstalk between pixel sensors of the pixel array.

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated chip (IC), including forming a plurality of image sensing elements including a first doping type within a substrate, performing a first removal process to form deep trenches within the substrate, the deep trenches separating the plurality of image sensing elements from one another, performing an epitaxial growth process to form an isolation epitaxial precursor including a first material within the deep trenches and to form a light absorbing layer including a second material different than the first material within the deep trenches and between sidewalls of the isolation epitaxial precursor, performing a dopant activation process on the light absorbing layer and the isolation epitaxial precursor to form a doped isolation layer including a second doping type opposite the first doping type, and filling remaining portions of the deep trenches with an isolation filler structure.

Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

Abstract: A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

Abstract: A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.