Patents by Inventor Yu-Hung Cheng

Yu-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10679859
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yu-Lin Liu, Ming-Hsien Lin, Tzo-Hung Luo
  • Publication number: 20200176306
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: August 21, 2019
    Publication date: June 4, 2020
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Publication number: 20200168583
    Abstract: A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Yu-Feng CHEN, Chun-Hung LIN, Han-Ping PU, Ming-Da CHENG, Kai-Chiang WU
  • Patent number: 10659983
    Abstract: A user equipment (UE) is configured with at least one bandwidth part (BWP) specific configuration information. The UE receives a configuration information specific to the bandwidth part (BWP). The configuration information configures an initial value of a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The UE starts or re-starts the BFD timer from the initial value when receiving a beam failure indication (BFI) from a lower sublayer, and counts a number of the received BFIs using a BFI counter. The UE resets the BFI counter to zero when receiving a reconfiguration information. The reconfiguration information, that is specific to the BWP, re-configures at least one of the initial value of the BFD timer and the BFI count threshold.
    Type: Grant
    Filed: March 9, 2019
    Date of Patent: May 19, 2020
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hung Wei, Chie-Ming Chou, Chien-Chun Cheng, Yu-Hsin Cheng, Hung-Chen Chen, Heng-Li Chin
  • Patent number: 10658410
    Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai
  • Publication number: 20200154469
    Abstract: A method for uplink transmission performed by a UE is provided. The method includes: receiving a first configured grant configuration that allocates a first PUSCH duration; receiving a second configured grant configuration that allocates a second PUSCH duration, wherein the second PUSCH duration overlaps with the first PUSCH duration; obtaining a first HARQ process ID for the first PUSCH duration, then determining whether a first configured grant timer associated with the first HARQ process ID is running; obtaining a second HARQ process ID for the second PUSCH duration, then determining whether a second configured grant timer associated with the second HARQ process ID is running; and selecting one of the first PUSCH duration and the second PUSCH duration for an uplink transmission based on whether the first configured grant timer is running and whether the second configured grant timer is running.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 14, 2020
    Inventors: HENG-LI CHIN, CHIA-HUNG WEI, WAN-CHEN LIN, YU-HSIN CHENG, CHIE-MING CHOU
  • Publication number: 20200144401
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion.
    Type: Application
    Filed: December 24, 2019
    Publication date: May 7, 2020
    Inventors: YU-HUNG CHENG, PO-JUNG CHIANG, YEN-HSIU CHEN, YEUR-LUEN TU
  • Publication number: 20200123352
    Abstract: An oxygen scavenging formulation comprising an oxidizable polymer resin, a transition metal catalyst, and a photosensitizer selected from one or more carotenoids is provided. The oxygen scavenging formulation does not need an additional triggering agent, or heating or light irradiation to trigger an oxygen scavenging function. A method of reducing oxygen atmosphere in a packaging article is also provided.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Applicant: FOOD INDUSTRY RESEARCH AND DEVELOPMENT INSTITUTE
    Inventors: YU-CHI CHENG, CHUN-FONG LIN, YI-JHEN WU, HSIU-HUNG JEN, BINGHUEI BARRY YANG
  • Publication number: 20200108592
    Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Publication number: 20200066768
    Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Yu-Hung Cheng, Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai
  • Patent number: 10569520
    Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates diametrically opposite to each other. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly placed above the pair of bonded substrates and configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Publication number: 20200051871
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Yu-Hung CHENG, Ching-Wei TSAI, Yeur-Luen TU, Tung-I LIN, Wei-Li CHEN
  • Patent number: 10553561
    Abstract: A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound. The method further includes providing a second semiconductor die package; and bonding the conductive elements of the first semiconductor die package to contacts on the semiconductor die package.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Publication number: 20200006385
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Yeur-Luen Tu, Min-Ying Tsai, Alex Usenko
  • Patent number: 10516040
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Po-Jung Chiang, Yen-Hsiu Chen, Yeur-Luen Tu
  • Publication number: 20190355560
    Abstract: A PVD reactor with a function of alignment in covering an upper cover includes a cavity having a first contact surface; an interior of the cavity having a metal isolation plate; an upper cover pivotally installed to the cavity; the upper cover having a second contact surface which is positioned corresponding to the first contact surface of the cavity; the upper cover being capable of being combined with a target; a plurality of semi-spherical recesses in the first contact surface of the cavity; and a plurality of semi-spherical protrusions in the second contact surface; when the upper cover covers upon the cavity, the plurality of semi-spherical protrusions will embed into the plurality of semi-spherical recesses.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Inventors: YING HSIEN CHENG, Yuan Yuan Song, Wei Chuan Chou, Hsin-Chih Chiu, Yu Hung Huang, Kuei Chang Peng
  • Publication number: 20190349120
    Abstract: A method for a user equipment (UE) is disclosed. The method includes receiving, by the UE, Downlink Control Information (DCI), the DCI containing an aperiodic channel state information (CSI) reporting configuration. The method also includes when the DCI is received by the UE during a Discontinuous Reception (DRX) operation mode, transmitting, by the UE, an aperiodic CSI report according to a transmission time indicated by the aperiodic CSI reporting configuration regardless of whether the transmission time for the CSI report is within active or non-active time periods of the DRX operation mode.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 14, 2019
    Inventors: CHIEN-CHUN CHENG, CHIA-HUNG WEI, YU-HSIN CHENG
  • Patent number: 10473714
    Abstract: A method for automated alignment between a plurality of electronic components and at least one testing device for receiving the electronic components for testing which includes defining a fiducial marker and positioning a moveable imaging device relative to a stationary imaging device, such that the fiducial marker is within a field of view of the moveable imaging device and within a field of view of the stationary imaging device. The moveable imaging device determines, with respect to each of the at least one testing device, a first offset between the testing device and the fidicual marker. The stationary imaging device determines, with respect to each electronic component, a second offset between the electronic component and the fidicual marker. Alignment is effected between each electronic component and the testing device in accordance with the first and second offsets.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 12, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chi Wah Cheng, Chi Hung Leung, Yu Sze Cheung, Kai Fung Lau
  • Patent number: 10453757
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen
  • Publication number: 20190281480
    Abstract: A user equipment (UE) is configured with at least one bandwidth part (BWP) specific configuration information. The UE receives a configuration information specific to the bandwidth part (BWP). The configuration information configures an initial value of a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The UE starts or re-starts the BFD timer from the initial value when receiving a beam failure indication (BFI) from a lower sublayer, and counts a number of the received BFIs using a BFI counter. The UE resets the BFI counter to zero when receiving a reconfiguration information. The reconfiguration information, that is specific to the BWP, re-configures at least one of the initial value of the BFD timer and the BFI count threshold.
    Type: Application
    Filed: March 9, 2019
    Publication date: September 12, 2019
    Inventors: CHIA-HUNG WEI, CHIE-MING CHOU, CHIEN-CHUN CHENG, YU-HSIN CHENG, HUNG-CHEN CHEN, HENG-LI CHIN