Patents by Inventor Yu-Hung Cheng

Yu-Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355560
    Abstract: A PVD reactor with a function of alignment in covering an upper cover includes a cavity having a first contact surface; an interior of the cavity having a metal isolation plate; an upper cover pivotally installed to the cavity; the upper cover having a second contact surface which is positioned corresponding to the first contact surface of the cavity; the upper cover being capable of being combined with a target; a plurality of semi-spherical recesses in the first contact surface of the cavity; and a plurality of semi-spherical protrusions in the second contact surface; when the upper cover covers upon the cavity, the plurality of semi-spherical protrusions will embed into the plurality of semi-spherical recesses.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Inventors: YING HSIEN CHENG, Yuan Yuan Song, Wei Chuan Chou, Hsin-Chih Chiu, Yu Hung Huang, Kuei Chang Peng
  • Publication number: 20190349120
    Abstract: A method for a user equipment (UE) is disclosed. The method includes receiving, by the UE, Downlink Control Information (DCI), the DCI containing an aperiodic channel state information (CSI) reporting configuration. The method also includes when the DCI is received by the UE during a Discontinuous Reception (DRX) operation mode, transmitting, by the UE, an aperiodic CSI report according to a transmission time indicated by the aperiodic CSI reporting configuration regardless of whether the transmission time for the CSI report is within active or non-active time periods of the DRX operation mode.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 14, 2019
    Inventors: CHIEN-CHUN CHENG, CHIA-HUNG WEI, YU-HSIN CHENG
  • Patent number: 10473714
    Abstract: A method for automated alignment between a plurality of electronic components and at least one testing device for receiving the electronic components for testing which includes defining a fiducial marker and positioning a moveable imaging device relative to a stationary imaging device, such that the fiducial marker is within a field of view of the moveable imaging device and within a field of view of the stationary imaging device. The moveable imaging device determines, with respect to each of the at least one testing device, a first offset between the testing device and the fidicual marker. The stationary imaging device determines, with respect to each electronic component, a second offset between the electronic component and the fidicual marker. Alignment is effected between each electronic component and the testing device in accordance with the first and second offsets.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 12, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chi Wah Cheng, Chi Hung Leung, Yu Sze Cheung, Kai Fung Lau
  • Patent number: 10453757
    Abstract: A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Ching-Wei Tsai, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen
  • Publication number: 20190281480
    Abstract: A user equipment (UE) is configured with at least one bandwidth part (BWP) specific configuration information. The UE receives a configuration information specific to the bandwidth part (BWP). The configuration information configures an initial value of a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The UE starts or re-starts the BFD timer from the initial value when receiving a beam failure indication (BFI) from a lower sublayer, and counts a number of the received BFIs using a BFI counter. The UE resets the BFI counter to zero when receiving a reconfiguration information. The reconfiguration information, that is specific to the BWP, re-configures at least one of the initial value of the BFD timer and the BFI count threshold.
    Type: Application
    Filed: March 9, 2019
    Publication date: September 12, 2019
    Inventors: CHIA-HUNG WEI, CHIE-MING CHOU, CHIEN-CHUN CHENG, YU-HSIN CHENG, HUNG-CHEN CHEN, HENG-LI CHIN
  • Publication number: 20190259655
    Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
  • Publication number: 20190221544
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20190220742
    Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
  • Patent number: 10354913
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Publication number: 20190207069
    Abstract: A light-emitting device includes a light body having an internal electrode layer, and a conductive layer. The conductive layer has a first portion formed on the internal electrode layer and overlapping the light body in a first direction, and a second portion overlapping the light body in a second direction. The first direction is perpendicular to the second direction.
    Type: Application
    Filed: March 11, 2019
    Publication date: July 4, 2019
    Inventors: Lung-Kuan LAI, Ching-Tai CHENG, Yih-Hua RENN, Min-Hsun HSIEH, Chun-Hung LIU, Shih-An LIAO, Ming-Chi HSU, Yu Chen LIAO
  • Patent number: 10340017
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 2, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai
  • Publication number: 20190172457
    Abstract: A notebook computer including a foldable body, a display unit, a touch pad, a keyboard, a first control unit, a wake-up unit, and a voice-assistant system, a second control unit electrically connected to the first control unit, the wake-up unit, and the voice-assistant system is provided. The first control unit is electrically connected to the display unit, the touch pad, and the keyboard. When the foldable body is in a folded and closed state, the display unit, the touch pad, and the keyboard are inactivated, the notebook computer is in a first mode. In the first mode, a user drives the wake-up unit to generate a wake-up signal being transmitted to the second control unit to activate the first control unit and the voice-assistant system. The notebook computer is transformed to a second mode, wherein the display unit, the touch pad, and the keyboard are still inactivated or sleeping.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Yu-Wen Cheng, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu, Chun-Wen Wang
  • Patent number: 10304723
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
  • Publication number: 20190157138
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.
    Type: Application
    Filed: February 26, 2018
    Publication date: May 23, 2019
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
  • Publication number: 20190148153
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary method includes forming a contact opening in a dielectric layer. The contact opening has sidewalls defined by the dielectric layer and a bottom defined by a conductive feature. An ALD-like nitrogen-containing plasma pre-treatment process is performed on the sidewalls (and, in some implementations, the bottom) of the contact opening. An ALD process is performed to form a titanium-and-nitrogen containing barrier layer over the sidewalls and the bottom of the contact opening. A cobalt-containing bulk layer is then formed over the titanium-and-nitrogen-containing barrier layer. A cycle of the ALD-like nitrogen-containing plasma pre-treatment process can include a nitrogen-containing plasma pulse phase and a purge phase. A cycle of the ALD process can include a titanium-containing pulse phase, a first purge phase, a nitrogen-containing plasma pulse phase, and a second purge phase.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 16, 2019
    Inventors: Chung-Liang Cheng, Yu-Lin Liu, Ming-Hsien Lin, Tzo-Hung Luo
  • Publication number: 20190139615
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Shaw-Hung KU, Yu-Hung HUANG, Cheng-Hsien CHENG, Chih-Wei LEE, Atsuhiro SUZUKI, Wen-Jer TSAI
  • Publication number: 20190131439
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.
    Type: Application
    Filed: April 24, 2018
    Publication date: May 2, 2019
    Inventors: YU-HUNG CHENG, PO-JUNG CHIANG, YEN-HSIU CHEN, YEUR-LUEN TU
  • Publication number: 20190118522
    Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates diametrically opposite to each other. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly placed above the pair of bonded substrates and configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 25, 2019
    Inventors: Chang-Chen Tsao, Kuo Liang Lu, Ru-Liang Lee, Sheng-Hsiang Chuang, Yu-Hung Cheng, Yeur-Luen Tu, Cheng-Kang Hu
  • Patent number: 10269864
    Abstract: Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Tung-I Lin, Wei-Li Chen, Yeur-Luen Tu
  • Publication number: 20190058070
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu