Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113660
    Abstract: The invention relates to a light emitting diode, which comprises a substrate and a semiconductor epitaxy structure. The semiconductor epitaxial structure is disposed on the substrate. The semiconductor epitaxial structure comprises semiconductor composite layers and a plurality of current spreading layers which are disposed among the semiconductor composite layers. The doping concentrations of the upper and lower adjacent current spreading layers are alternately high and low.
    Type: Application
    Filed: August 16, 2024
    Publication date: April 3, 2025
    Inventors: Yu-Ling Cheng, Po-Jen Hsieh, Tzu-Wen Wang, Yi-Jen Lin
  • Publication number: 20250113495
    Abstract: A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.
    Type: Application
    Filed: October 26, 2023
    Publication date: April 3, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Patent number: 12264979
    Abstract: A force sensing device is mounted on a tool to sense force, particularly quasi-static and static forces. The force sensing device includes at least one a sensor. A piezoelectric element in the sensor includes a driving portion and a sensing portion. A first voltage is input to the driving portion to generate a vibration in the piezoelectric element and a second voltage in response to the vibration is output from the sensing portion. The second voltage output from the sensing portion is changed as the vibration in the piezoelectric element is suppressed by an external force acting on the force sensing device so variation of the second voltage can be used to measure the external force.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 1, 2025
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Yu-Jen Wang, Yu-Jan Lo, Ren-Yi Huang
  • Publication number: 20250098156
    Abstract: A method for forming a semiconductor structure includes the following steps. A first trench is formed in a semiconductor substrate, and a first nitride layer is formed along a sidewall and a bottom surface of the first trench. A first oxide layer is formed over the first nitride layer to fill the first trench, and the first oxide layer is recessed from the first trench to form a first recess. A portion of the first nitride layer exposed from the first recess is etched, and a second nitride layer is formed along a sidewall and a bottom surface of the first recess. The second nitride layer includes a first portion along the bottom surface and a second portion along the sidewall. The second portion is removed, and a second oxide layer is formed over the first portion to fill the first recess.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Wei-Che CHANG, Kai JEN, Yu-Po WANG
  • Patent number: 12255095
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Patent number: 12253506
    Abstract: A method of building upstream-and-downstream configuration of sensors includes determining two sets of geographic position data of a target sensor and a candidate sensor, obtaining pollution-associated periods according to pieces of flow field data, the sets of geographic position data and pieces of target sensing data of the target sensor to determine a pollution-associated period, calculating a correlation between target sensing data obtained by the target sensor during the pollution-associated period and candidate sensing data obtained by the candidate sensor during the associated air pollution period to obtain sensor correlations, and determining the target sensor and the candidate sensor having a upstream-and-downstream relationship with the candidate sensor being used as a satellite sensor of the target sensor when a quantity ratio of sensor correlations being larger than or equal to a correlation threshold is larger than or equal to a default ratio.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: March 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin Wang, Guang-Huei Gu, Chih-Jen Chen
  • Publication number: 20250087625
    Abstract: A zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. The single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. The one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. The uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. In this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.
    Type: Application
    Filed: January 11, 2024
    Publication date: March 13, 2025
    Inventors: Yu-Young WANG, Chun-Min LIN, Min-Yu WU, Chih-Jen WU
  • Publication number: 20250089578
    Abstract: A magnetic tunnel junction (MTJ) structure and a memory cell are provided. The MTJ includes a barrier layer, a free layer and a metal oxide cap layer. The free layer is disposed on the barrier layer. The metal oxide cap layer is disposed on the free layer. The metal oxide cap layer has a first surface and a second surface opposite to the first surface. The first surface of the metal oxide cap layer is in contact with the free layer. In a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhi-Ren Xiao, Nuo Xu, Po-Sheng Lu, Yuan-Hao Chang, Zhiqiang Wu, Yu-Jen WANG
  • Publication number: 20250079177
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
    Type: Application
    Filed: November 7, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: En-Ping LIN, Yu-Ling KO, I-Chung WANG, Yi-Jen CHEN, Sheng-Kai JOU, Chih-Teng LIAO
  • Patent number: 12245516
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Vignesh Sundar, Yu-Jen Wang
  • Patent number: 12237398
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Yu-Ren Wang, Ying-Wei Yen, Fu-Jung Chuang, Ya-Yin Hsiao, Nan-Yuan Huang
  • Publication number: 20250044636
    Abstract: An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Yi-hsin Lin, Ting-Wei Huang, Yu-Jen Wang
  • Patent number: 12216326
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 4, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiang-Chin Lin, Shou-Jen Liu, Guan-Bo Wang, Kai-Po Fan, Chan-Jung Hsu, Shao-Chung Chang, Shih-Wei Hung, Ming-Chun Hsieh, Wei-Pin Chin, Sheng-Zong Chen, Yu-Huai Liao, Sin-Hong Lin, Wei-Jhe Shen, Tzu-Yu Chang, Kun-Shih Lin, Che-Hsiang Chiu, Sin-Jhong Song
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20250025805
    Abstract: A party popper contains: a cylinder, a sealing element, a drive element, a flexible fitting element, and a weaken structure. The cylinder includes a first segment and a second segment. The sealing element is a film and is configured to close the second segment. The multiple streamers are filled in the cylinder. A diameter of the drive element is equal to a diameter of the cylinder. The flexible fitting element is made of flexible material with low elastic modulus, and the flexible fitting element includes a cap, a neck section, and a head. The weaken structure surrounds the neck section, and a pulling length is defined to pull off the weaken structure by pulling the weaken structure from the head to the neck section and the cap, such that the weaken structure is pulled off to remove the neck section and the head from the cap.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventor: Yu-Jen Wang
  • Patent number: 12207567
    Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 12204199
    Abstract: An optical subassembly for switchably focusing or redirecting a light beam may include a polarization element having a polarization-selective beam redirection/focusing property, a first switchable polarization rotator upstream of the polarization element, and a second switchable polarization rotator downstream of the polarization element. A polarizer may be provided immediately downstream of the second switchable polarization rotator. The first and second switchable polarization rotators may be operated in counterphase, so as to mutually offset dependence of angle and wavelength characteristics of the polarization rotators on the switching state of the polarization rotators.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: January 21, 2025
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Yu-Jen Wang, Xinyu Zhu, Chulwoo Oh, Sawyer Miller
  • Patent number: 12203266
    Abstract: A construction combination includes a construction member, and an acoustic absorbing device engaged in the construction member for absorbing acoustic sounds. The acoustic absorbing device includes a housing engaged in the construction member, and a casing engaged in the housing. The housing includes one or more couplers, and the casing includes one or more connectors for engaging with the couplers and for anchoring the casing in the housing. A sound absorbing member is engaged in the casing, and the sound absorbing member includes an anchor for engaging with the casing and for anchoring the sound absorbing member in the casing.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: January 21, 2025
    Assignee: WISWONG TECHNOLGOY CORPORATION
    Inventors: Hong Jen Wang, Yu Ming Wang, Kai I Wang
  • Patent number: 12185638
    Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Yu-Jen Wang
  • Patent number: 12185641
    Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Vignesh Sundar, Yu-Jen Wang, Dongna Shen, Sahil Patel, Ru-Ying Tong