Patents by Inventor Yu-Jen Wang

Yu-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10777590
    Abstract: A method for forming an image sensor device structure is provided. The method includes forming a light-sensing region in a substrate, and forming an interconnect structure below a first surface of the substrate. The method also includes forming a trench in the light-sensing region from a second surface of the substrate, and forming a doping layer in the trench. The method includes forming an oxide layer in the trench and on the doping layer to form a doping region, and the doping region is inserted into the light-sensing region.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Yu-Jen Wang, Shyh-Fann Ting, Wei-Chuang Wu, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10770654
    Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Publication number: 20200279917
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200270737
    Abstract: A MgO layer is formed using a process flow wherein a Mg layer is deposited at a temperature <200° C. on a substrate, and then an anneal between 200° C. and 900° C., and preferably from 200° C. and 400° C., is performed so that a Mg vapor pressure >10?6 Torr is reached and a substantial portion of the Mg layer sublimes and leaves a Mg monolayer. After an oxidation between ?223° C. and 900° C., a MgO monolayer is produced where the Mg:O ratio is exactly 1:1 thereby avoiding underoxidized or overoxidized states associated with film defects. The process flow may be repeated one or more times to yield a desired thickness and resistance x area value when the MgO is a tunnel barrier or Hk enhancing layer. Moreover, a doping element (M) may be added during Mg deposition to modify the conductivity and band structure in the resulting MgMO layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Sahil Patel, Guenole Jan, Yu-Jen Wang
  • Patent number: 10756137
    Abstract: A MTJ stack comprising at least a pinned layer, a barrier layer, and a free layer is deposited on a bottom electrode. A top electrode layer, a carbon-based hard mask, and a dielectric hard mask are deposited in order on the MTJ stack. First, the hard masks and MTJ stack are etched. The etched MTJ stack has a first width. During the first etching, chemical damage forms on sidewalls of the MTJ stack. Next, the carbon-based hard mask is trimmed to a second width smaller than the first width. Then in a second etching, the top electrode and free layer of said MTJ stack not covered by the trimmed carbon-based hard mask are etched to complete formation of the MTJ structure wherein during the second etching of the free layer, chemical damage is removed from the free layer and metal re-deposition is formed on sidewalls of the free layer.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 25, 2020
    Assignee: Headway Technologies, Inc.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10754201
    Abstract: A liquid crystal photoelectric apparatus including an upper substrate, a lower substrate, a plurality of alignment layers, and a liquid crystal material is provided. The alignment layers include an upper alignment layer, a lower alignment layer, and at least one intermediate alignment layer. The upper alignment layer has a first orientation direction. The lower alignment layer has a second orientation direction. The at least one intermediate alignment layer has an intermediate orientation direction. The intermediate orientation direction is between the first orientation direction and the second orientation direction. The liquid crystal material includes a plurality of liquid crystal material portions. Each of the liquid crystal material portions is disposed between any adjacent two alignment layers. A manufacturing method of the liquid crystal photoelectric apparatus is also provided.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 25, 2020
    Assignees: National Tsing Hua University, Advanced Comm. Engineering Solution Co., Ltd.
    Inventors: Ci-Ling Pan, Anup Kumar Sahoo, Chun-Ling Yen, Chan-Shan Yang, Yi-Hsin Lin, Hung-Chun Lin, Yu-Jen Wang
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200249379
    Abstract: A lens including a filter, an aperture stop, and a lens set sequentially arranged along a first direction is provided. The filter includes a central region and a peripheral region. The central region has a first light transmission band for a wavelength range of a visible light and a second light transmission band for a wavelength range of an infrared light. The peripheral region surrounds the central region. The peripheral region has a third light transmission band for the wavelength range of the infrared light and is substantially opaque to the visible light, and an area of one portion of the central region surrounded by the peripheral region is tapered toward the first direction.
    Type: Application
    Filed: November 14, 2019
    Publication date: August 6, 2020
    Applicant: Rays Optics Inc.
    Inventors: Chen-Cheng Lee, Chen-Yi Tsai, Shin-Jen Wang, Kuo-Hsiang Hung, Chih-Ling Lin, Meng-Wei Lin, Yu-Chia Lu
  • Publication number: 20200243664
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 30, 2020
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Publication number: 20200243125
    Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15 V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 30, 2020
    Inventors: Hideaki Fukuzawa, Vignesh Sundar, Yu-Jen Wang, Ru-Ying Tong
  • Publication number: 20200243582
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: SHENG-CHAN LI, I-NAN CHEN, TZU-HSIANG CHEN, YU-JEN WANG, YEN-TING CHIANG, CHENG-HSIEN CHOU, CHENG-YUAN TSAI
  • Patent number: 10718989
    Abstract: An electrically tunable focusing achromatic lens includes a first liquid crystal cell, a second liquid crystal cell, and first and second electrode layer units which have two predetermined patterns for permitting two predetermined radially varying electric fields to be generated to across the first and second liquid crystal cells, respectively, to thereby allow one of the first and second liquid crystal cells to acquire a predetermined positive optical power and the other one of the first and second liquid crystal cells to acquire a predetermined negative optical power. When an incident light passes through the first and second liquid crystal cells, chromatic aberration of the first liquid crystal cell can be counterbalanced by that of the second liquid crystal cell.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 21, 2020
    Assignee: National Chiao Tung University
    Inventors: Yu-Jen Wang, Hung-Chun Lin, Yi-Hsin Lin
  • Patent number: 10714680
    Abstract: A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10714679
    Abstract: An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60 nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Zhongjian Teng, Yu-Jen Wang
  • Patent number: 10707282
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. An organic layer including planarization layers and a pixel definition layer may overlap the thin-film circuitry. Thin-film encapsulation may overlap the organic layer. The thin-film encapsulation may be formed from an organic dielectric layer interposed between two layers of inorganic dielectric material. A strip of peripheral crack-stopper structures may run along an edge of the display and may surround the array of pixels. The crack-stopper structures may include parallel inorganic lines formed from a first inorganic layer such as an inorganic layer of the thin-film circuitry. A strip of the organic layer may overlap the parallel inorganic lines. The crack-stopper structures may have parallel tapered polymer lines. The polymer lines may be overlapped by a second inorganic dielectric layer formed from the inorganic material of the thin-film encapsulation layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Chih Jen Yang, Prashant Mandlik, Chia-Hao Chang, Chien-Chung Wang, Te-Hua Teng, Yu Cheng Chen
  • Publication number: 20200212297
    Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Yi Yang, Vignesh Sundar, Dongna Shen, Sahil Patel, Ru-Ying Tong, Yu-Jen Wang
  • Publication number: 20200212298
    Abstract: A MTJ stack is deposited on a bottom electrode, the stack comprising at least a pinned layer, a barrier layer, a free layer, and a top electrode layer. The top electrode and MTJ stack are etched where not covered by a photoresist pattern to form an MTJ structure. A conformal encapsulation dielectric is deposited over the MTJ structure. A magnetic metal layer is deposited on the encapsulation dielectric and anisotropically etched leaving a magnetic metal shield on sidewalls of the MTJ structure. A dielectric layer is deposited over the magnetic metal shield and MTJ structure. The dielectric layer and encapsulation dielectric are polished away to expose the top electrode. A top metal contact layer is deposited contacting the top electrode and the magnetic metal shield wherein the magnetic metal shield has no contact with said bottom electrode and MTJ structure but is separated from them by the encapsulation dielectric.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Yi Yang, Guenole Jan, Yu-Jen Wang
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Patent number: 10700269
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Publication number: 20200203167
    Abstract: The semiconductor structure includes first and second active regions arranged in a first grid oriented in a first direction. The semiconductor structure further includes gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction. The first and second active regions are separated, relative to the second direction, by a gap. Each gate electrode includes a first segment and a gate extension. Each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT?150 nanometers (nm). Each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular.
    Type: Application
    Filed: August 30, 2019
    Publication date: June 25, 2020
    Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG