Abstract: A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: An illumination system is provided. The illumination system includes a light source assembly configured to output a first polarized light having a first handedness. The illumination system also includes a light guide plate configured to guide the first polarized light received from the light source assembly and output a second polarized light having a second handedness opposite to the first handedness. The light guide plate includes two wedges coupled to one other at a slanted surface between the two wedges and a reflective polarizer disposed at the slanted surface. The illumination system also includes a reflective sheet arranged at a first side surface of the light guide plate and configured to reflect the first polarized light as the second polarized light. The reflective polarizer includes a birefringent material having a chirality, and is configured to selectively transmit the first polarized light and reflect the second polarized light.

Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: A force sensor includes a sensing element, a forced element and strain gauges. There are flexure mechanisms on the sensing element, the forced element is coupled to a free end of each of the flexure mechanisms, and each of the strain gauges is placed on an elastic portion of each of the flexure mechanisms respectively. Each of the strain gauges is provided to detect an elastic strain of the elastic portion when a forced is applied to the forced element, transmitted to the free end via the forced element and transmitted to the elastic portion via a flexure hinge of each of the flexure mechanisms.

Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.

Abstract: A complementary metal oxide semiconductor (CMOS) device comprises a first metal line, a first metal via on the first metal line, a magnetic tunneling junction (MTJ) device on the first metal via wherein the first metal via acts as a bottom electrode for the MTJ device, a second metal via on the MTJ device, and a second metal line on the second metal via.

Abstract: An optical device is provided. The optical device includes a first optical element configured to output an elliptically polarized light having one or more predetermined polarization ellipse parameters. The optical device also includes a second optical element including a birefringent material with a chirality, and configured to receive the elliptically polarized light from the first optical element and reflect the elliptically polarized light as a circularly polarized light.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.

Abstract: An intake swirl gasket is disclosed herein. It is installed between a cylinder head and an intake manifold and comprises plural airflow holes for respectively communicating with plural intake passages of the cylinder head; and plural diversion devices respectively disposed in the plural airflow holes and each having an axis and plural splitter blades extended from the axis for connecting to an inner wall of each of the plural airflow holes, wherein each of the plural splitter blades is shaped as an arc to form a recessed surface towards the intake manifold at one side thereof and a convex surface towards the cylinder head at the other side thereof, and wherein an included angle between each of the plural splitter blades and an end face of the intake swirl gasket oriented towards the cylinder head ranges from 50 to 80 degrees.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.

Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Abstract: A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.