Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

Abstract: The present invention relates to a naphthalimide sulfonate derivative, and a photoacid generator and a photoresist composition each comprising same and, more specifically, to a naphthalimide sulfonate derivative compound, and a photoacid generator and a photoresist composition each comprising same, wherein the compound has excellent absorbance for light of i-line (365 nm) wavelength, is greatly easy to prepare into a polymerizable composition due to very high solubility in an organic solvent, has good thermal stability, and shows a favorable acid generation rate.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A fan guard for a fan container includes a housing and a plurality of wings. The housing has a hollow interior defined by a cylindrical inner surface. The housing extends longitudinally between a first housing end and a second housing end. The plurality of wings is positioned within the hollow interior of the housing. Each wing of the plurality of wings extends radially, from a center of symmetry of the cylindrical inner surface to the cylindrical inner surface. Each wing of the plurality of wings is radially curved between the first housing end and the second housing end.

Abstract: Disclosed is a method of integrally optimizing different types of parameters that require setting during a machine learning process. The disclosed method of integrally optimizing the parameters includes performing training on a machine learning model by selecting sensor parameters and machine learning model hyperparameters until a predetermined termination condition is satisfied; and determining, among the selected sensor parameters and machine learning model hyperparameters, an optimized sensor parameter and optimized machine learning model hyperparameter that minimize a loss value for the machine learning model, wherein the performing of the training on the machine learning model includes selecting the sensor parameters and machine learning model hyperparameters that satisfy a predetermined optimization range, and performing training on the machine learning model based on sensor data provided from a sensor by the selected sensor parameters and the machine learning model hyperparameters.

Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: Disclosed herein are a reasoning method based on a structural attention mechanism for knowledge-based question answering and a computing apparatus for performing the reasoning method. The reasoning method includes: recognizing one or more entities in a query including content and a question, and linking the recognized entities to a knowledge base; constructing a question hypergraph and a query-aware knowledge hypergraph by performing a multi-hop graph walk on a question graph and the knowledge base; and inferring a correct answer to the question by applying as attention mechanism to a query hyperedge and a knowledge hyperedge included in the question hypergraph and the query-aware knowledge hypergraph, respectively.

Abstract: A battery charging apparatus includes a battery compartment having a receptacle that is configured to receive a battery pack. The battery charging apparatus includes a first heat exchange module and/or a second heat exchange module. The first heat exchange module includes a plenum surrounding the receptacle, where the plenum includes a chamber to receive a fluid. The plenum also includes a plurality of flow guides disposed in the chamber to define a variable flow passage for the fluid. The second heat exchange module includes a battery connector and a heat sink thermally coupled to the battery connector. The heat sink is arranged to dissipate thermal energy from the battery pack.

Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Abstract: Provided is an herbal composition including an extract from an herbal raw material including at least one of Artemisia argyi, Ohwia caudata, Anisomeles indica (L.) O. Ktze, Ophiopogon japonicus, Houttuynia cordata, Platycodon grandiflorus, Glycyrrhiza uralensis, Perilla frutescens, and chrysanthemum. Also provided is a method for preparing the herbal composition and a method for preventing or treating a viral infection by administering an effective amount of the herbal composition to a subject in need thereof.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

Abstract: A microfluidic chip suitable for controlling movement and detecting position of a microfluid includes a first substrate, a second substrate, first scan lines, first signal lines, second scan lines, second signal lines, actuating units, and heating units. The first scan lines and the first signal lines are disposed on the first substrate. The second scan lines and the second signal lines are disposed on the second substrate. The actuating units each have a first active device and a driving electrode. The first active device is electrically connected to one of the first scan lines, one of the first signal lines, and the driving electrode. The heating units are respectively disposed corresponding to the actuating units, and each have a second active device and a negative temperature coefficient thermistor. The second active device is electrically connected to one of the second scan lines and one of the second signal lines.

Abstract: A method for making an integrated circuit (IC) includes inserting black boxes into a layout of the IC; connecting the black boxes with a connectivity network; and inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network. After the inserting of the first dummy patterns, the method further includes replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area. In the method, at least one of the following operations is performed by an electronic design automation (EDA) tool: the inserting of the black boxes, the connecting of the black boxes, the inserting of the first dummy patterns, and the replacing of the black boxes with the circuit macros.

Abstract: A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.