Patents by Inventor Yu Jung

Yu Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230038144
    Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.
    Type: Application
    Filed: August 27, 2021
    Publication date: February 9, 2023
    Applicant: I-SHOU UNIVERSITY
    Inventors: Yu-Jung Huang, Mong-Na Lo Huang, Tzu-Lun Yuan, Mei-Hui Guo
  • Publication number: 20230037670
    Abstract: Provided are an image acquisition device which increases a small depth of field of an objective lens to acquire a high depth of field image and an image acquisition method using the same. The image acquisition device according to an exemplary embodiment of the present disclosure is an image acquisition device which acquires an image of a subject including an image collection unit; and an objective lens unit disposed below the image collection unit, and the image collection unit generates an image in which Z-axis signals are superposed within a range corresponding to a thickness of the subject, in an area to be captured of the subject.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 9, 2023
    Applicant: VIEWORKS CO., LTD.
    Inventors: Hyun Suk JANG, Yu Jung KANG, Min Gyu JIN
  • Patent number: 11550986
    Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Yu-Jung Chang, Hui-Zhong Zhuang, Ting-Wei Chiang
  • Publication number: 20230006109
    Abstract: A light emitting device and a manufacturing method thereof are provided. The light emitting device includes a light emitting unit, a fluorescent layer, a reflective layer, and a light-absorbing layer. The light emitting unit has a top surface, a bottom surface opposite to the top surface, and a side surface located between the top surface and the bottom surface. The light emitting unit includes an electrode disposed at the bottom surface. The fluorescent layer is disposed on the top surface of the light emitting unit. The reflective layer covers the side surface of the light emitting unit. The light-absorbing layer covers the reflective layer, so that the reflective layer is located between the side surface of the light emitting unit and the light-absorbing layer.
    Type: Application
    Filed: June 24, 2022
    Publication date: January 5, 2023
    Applicant: Genesis Photonics Inc.
    Inventors: Yun-Han Wang, Chin-Hua Hung, Chuan-Yu Liu, Tsai-Chieh Shih, Jui-Fu Chang, Yu-Jung Wu, Yu-Feng Lin
  • Publication number: 20230005155
    Abstract: A high depth of field image generating apparatus according to the present disclosure includes a region segmentation unit which segments a region for a stereo image to generate region data, a depth estimating unit which estimates depths for the stereo image to generate depth data, and a high depth of field image generating unit which generates a high depth of field image from the stereo image, the region data, and the depth data.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 5, 2023
    Applicant: VIEWORKS CO., LTD.
    Inventors: Yu Jung KANG, Min Gyu JIN
  • Publication number: 20220414309
    Abstract: A method that includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block has a corner, adding first patterns along a first edge of the corner, adding second patterns along a second edge of the corner, moving a first column of the first patterns closest to the second edge horizontally toward the second edge, moving a second column of second patterns closest to the second edge horizontally toward the second edge, extending lengths of the first and second patterns in the first and second columns, and outputting a pattern layout in a computer-readable format, where the pattern layout includes the first patterns and the second patterns.
    Type: Application
    Filed: December 30, 2021
    Publication date: December 29, 2022
    Inventors: Yung Feng Chang, Pi-Yun Sun, Tung-Heng Hsieh, Yu-Jung Chang, Bao-Ru Young
  • Publication number: 20220399269
    Abstract: An IC device includes an interlayer dielectric (ILD), a first tower structure embedded in the ILD, and a first ring region including a portion of the ILD that extends around the first tower structure. The first tower structure includes a plurality of first conductive patterns in a plurality of metal layers, and a plurality of first vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of first conductive patterns and the plurality of first vias are coupled to each other to form the first tower structure. The plurality of first conductive patterns is confined by the first ring region, without extending beyond the first ring region. The first tower structure is a dummy tower structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: December 15, 2022
    Inventors: Yu-Jung CHANG, Nien-Yu TSAI, Min-Yuan TSAI, Wen-Ju YANG
  • Patent number: 11523208
    Abstract: The present disclosure provides an ear tip. The ear tip includes a main body, a first conductive element at least partially embedded in the main body, a second conductive element at least partially embedded in the main body and spaced apart from the first conductive element. The main body includes a central portion having a top and a tail portion extending from the top of the central portion. The first conductive element is proximal to the top of the central portion and the second conductive element is distal from the top of the central portion. A wearable device is also disclosed.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: December 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Tau Huang, Yu-Jung Chang
  • Publication number: 20220384416
    Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
  • Patent number: 11508661
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Patent number: 11507509
    Abstract: A memory system may transfer a reference write size for a memory device to a host, and, when receiving, from the host, a write request for first data having a size corresponding to a multiple of the reference write size, may directly write the first data to the memory device without caching the first data in a write cache.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Do Hyeong Lee, Yu Jung Lee, Min Kyu Choi
  • Publication number: 20220350826
    Abstract: A question answering method that is performed by a question answering apparatus includes: receiving a data set including video content and question-answer pairs; generating input time-series sequences from the video content of the input data set and also generating a question-answer time-series sequence from the question-answer pair of the input data set; calculating weights by associating the input time-series sequence with the question-answer time-series sequence and also calculating first result values by performing operations on the calculated weights and the input time-series sequences; calculating second result values by paying attention to portions of the input time-series sequences that are directly related to characters appearing in questions and answers; and calculating third result values by concatenating the time-series sequences, the first result values, the second result values, and Boolean flags and selecting a final answer based on the third result values.
    Type: Application
    Filed: November 18, 2020
    Publication date: November 3, 2022
    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byoung-Tak ZHANG, Seongho CHOI, Kyoung-Woon ON, Yu-Jung HEO, You Won JANG, Ahjeong SEO, Seungchan LEE, Minsu LEE
  • Patent number: 11486433
    Abstract: A self-drilling screw includes a leading section having a drill body and opposite discharge grooves formed on the drill body. The drill body and the discharge grooves meet at cutting edges. On the drill body are formed two blade portions connected to the cutting edges and tapering at respective second tips. The blade portion has a second included angle of not more than 50 degrees. Between the blade portions is formed a drilling portion terminating at a first tip and having a first included angle of not more than 60 degrees. Two opposite concave surfaces each extend from the drilling portion to each blade portion. The first tip and the second tips are situated at different places. Accordingly, the end of the leading section presents a shape of a curved bow riser to cut quickly and help quick removal of chips, thereby decreasing resistance and preventing the cracking problem.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Shan Yin International Co., Ltd.
    Inventors: Kou-Tsair Su, Yu-Jung Su
  • Publication number: 20220338746
    Abstract: A pulse sensor and a pulse sensing system are provided. The pulse sensor includes a pressure sensing circuit, a reference circuit, and an output circuit. The pressure sensing circuit may sense a pulse vibration to generate a sensing signal. The reference circuit may generate a reference signal according to a base signal. A first input terminal of the output circuit is coupled to the pressure sensing circuit. A second input terminal of the output circuit is coupled to the reference circuit. The output circuit generates a pulse sensing current at an output terminal of the output circuit according to a difference between the sensing signal and the reference signal.
    Type: Application
    Filed: November 4, 2021
    Publication date: October 27, 2022
    Applicant: Au Optronics Corporation
    Inventors: Ming-I Huang, Yu-Jung Liu, Chien Cheng Wang
  • Publication number: 20220313099
    Abstract: The present disclosure provides a wearable device. The wearable device includes a first sensing element configured to be disposed adjacent to a right ear of a user while the wearable device is worn by the user and a second sensing element configured to be disposed adjacent to a left ear of the user and coupled to the first sensing element while the wearable device is worn by the user. The second sensing element and the first sensing element are configured to sense a biological signal from the user. The wearable device also includes a reference electrode configured to reduce an interference to the biological signal. A headset device and a method for operating a wearable device is also provided in the present disclosure.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Jung CHANG, Ming-Tau HUANG
  • Publication number: 20220313163
    Abstract: The present disclosure provides a wearable device. The wearable device includes a first element and a second element. The first element is configured to sense a bio-signal from a user. The second element is configured to transmit the bio-signal to a processor. The second element has a first surface and a second surface non-coplanar with the first surface. The first element is in contact with the first surface and the second surface of the second element.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Jung CHANG, Ming-Tau HUANG
  • Publication number: 20220300196
    Abstract: A memory system may include a memory device including at least one sequential area in which a data corresponding to consecutive logical addresses of the at least one sequential area is stored, a sequential buffer configured to temporarily store the data to be stored in the at least one sequential area, a meta buffer configured to store a meta data including a write pointer information indicating a logical address in which data is to be stored from among logical addresses corresponding to the at least one sequential area, and an area state information indicating whether the sequential buffer is allocated to the at least one sequential area, and a memory controller configured to perform a write operation of storing the data in the at least one sequential area in response to a first command received from the host using the meta data.
    Type: Application
    Filed: August 27, 2021
    Publication date: September 22, 2022
    Inventors: Do Hyeong LEE, Yu Jung LEE, Min Kyu CHOI
  • Publication number: 20220291658
    Abstract: A production line scheduling method, adapted to a plurality of jobs passing a bottleneck station having at least one manufacturing machine, the jobs respectively correspond to a plurality of job conditions, and the method comprises: performing a plurality of times of a schedule simulation algorithm on the jobs to sequentially establish a plurality of schedule simulation trees, and obtaining a job schedule and a simulated finishing period of each job based on the schedule simulation trees, wherein each schedule simulation tree comprises at least one scheduling route, and each scheduling route is generated from one schedule simulation algorithm; and calculating a plurality of expected feeding times of each job at a plurality of stations comprising the bottleneck station, wherein the schedule simulation algorithm comprises: performing a node expansion step based on at least one node expansion condition and the job conditions to obtain the scheduling route.
    Type: Application
    Filed: July 9, 2021
    Publication date: September 15, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Jung YEH, Tsan-Cheng SU, Chung-Wei LIN
  • Publication number: 20220268969
    Abstract: Disclosed is a light diffusing lens installed to cover an LED package mounted on a substrate, including a bottom surface which is an ellipse having a semi major axis and a semi minor axis, and a top surface which has a dome-shaped structure, wherein a Z segment function f(a) of the top surface line segment in a diagonal radius direction between the semi major axis and the semi minor axis is specified.
    Type: Application
    Filed: March 19, 2021
    Publication date: August 25, 2022
    Inventors: Seok Chae KO, Jae Yu JUNG, Kang Hyun LEE
  • Patent number: D968568
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: November 1, 2022
    Assignee: T & R ROXGEN INDUSTRIES CO., LTD.
    Inventor: Yu-Jung Shih