Abstract: Provided is an image acquisition apparatus capable of acquiring a clear and high-resolution stereo image by increasing the depth of field for a thick subject or a subject with inconsistent thickness. An image acquisition apparatus according to an exemplary embodiment of the present invention includes: a polarizing prism unit for splitting an incident light beam; and a plurality of image collecting units for collecting the split light beam from the polarizing prism unit, in which the polarizing prism unit includes: a first polarization unit having a first polarization angle obtained by adding half a binocular parallax angle of a person to 45°, and a second polarization unit disposed to be in contact with the first polarization unit and having a second polarization angle obtained by subtracting half of the binocular parallax angle of a person from 45°.

Abstract: A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A head-mounted device for reducing symptoms of cybersickness includes a main shell, and a stimulation unit. The main shell includes first, second and third tube bodies that are arc-shaped and that are worn respectively on the top and back of the user’s head and the user’s ear. The stimulation unit includes first, second and third components that are received respectively in the first, second and third tube bodies, that are movable in a rolling, sliding or flowing manner with low friction, and that are configured to generate and transmit a stimulation force, through one end of the respective one of the first, second and third tube bodies, to the use’s vestibular system in respond to movement of the user’s head.

Abstract: Provided is an image acquisition device including: a stage on which a slide is mounted; an objective lens disposed to face a sample; a beam split unit separating light from the sample, which is incident through the objective lens into at least two, and delivering the separated lights; at least two image sensor units acquiring an image of the sample from the lights separated by the beam split unit; an image generation unit synthesizing the image acquired from the image sensor unit and generating the synthesized image; and a main control unit controlling operations of the stage or the objective lens, and the image sensor unit and the image generation unit, in which the stage is movable relatively to an optical axis of the objective lens at least in a first direction, and the at least two image sensor units acquire images at different focus positions for the sample.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A semiconductor device having a standard cell comprises a first bottom transistor, a first top transistor, a second bottom transistor, a second top transistor, and a first bottom-transistor-level metal line. The first bottom transistor is in a first row. The first top transistor is disposed above the first bottom transistor in the first row. The first bottom transistor and the first top transistor share a first gate structure. The second bottom transistor is in a second row next to the first row. The second top transistor is disposed above the second bottom transistor in the second row. The second bottom transistor and the second top transistor share a second gate structure. The first bottom-transistor-level metal line extends laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

Abstract: Apparatuses, systems, and techniques to modify tensors based on processor requirements. In at least one embodiment, input tensors and weight tensors are modified to meet processing resource requirements.

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A pushing force-actuated braking device includes an annular housing that houses a brake disc, a braking piston, plural braking elements, and a brake-releasing piston. When only the braking piston is under the action of a fluid, the braking piston applies an axial pushing force to the brake disc such that the brake disc is kept at a braking position jointly by the braking piston and the braking elements. When only the brake-releasing piston is under the action of a fluid, the brake-releasing piston applies an opposite pushing force to the brake disc to keep it at a brake-releasing position. Should the fluid acting on the braking piston fail, the force of the braking elements still enables the brake disc to produce a braking effect. The pushing force-actuated braking device has a modular design to facilitate assembly and disassembly. A rotary table using the braking device is also provided.

Abstract: The present invention provides a transceiver circuit including a transmitter circuit, a frequency synthesizer and control circuit. The transmitter circuit is configured to generate a transmission signal, wherein the transmission signal is transmitted through an antenna. The frequency synthesizer is configured to generate a clock signal for the transmitter circuit to generate the transmission signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to make the frequency synthesizer have a first loop bandwidth; and after a period of time after the transceiver circuit is switched from the standby mode to a transmission mode, the control circuit generates the first control signal to make the frequency synthesizer have a second loop bandwidth.

Abstract: A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.

Abstract: A coil component includes a body including a first surface and a plurality of side surfaces respectively connected to the first surface, a substrate disposed in the body, a coil portion disposed in the body, a lead-out portion disposed in the body and connected to the coil portion, and a dummy portion spaced apart from the lead-out portion. The body includes four corners, at each of which two adjacent side surfaces of the first to fourth side surfaces are in contact with each other, and the dummy portion includes first to fourth dummy patterns respectively disposed outside the coil portion and extending toward the four corners of the body.

Abstract: Provided is a pre-conditioned mesenchymal stem cell (MSC), an exosome derived therefrom, and a cell-protective composition including the pre-conditioned MSC or the exosome. Also provided is a method for preparing the pre-conditioned MSC by contacting an MSC with an effective amount of ginkgolide A. Still provided is a method for promoting recovery or reducing death of damaged nerve cells, including administering to the damaged nerve cells a composition including the pre-conditioned MSC or the exosome.

Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active regions extend in a first direction, are in a substrate, and are located on a first level. The first active region includes a first drain/source region and a second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact extends in a second direction, overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact extends in at least the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first drain/source region, is electrically coupled to the third drain/source region, and is located on a third level.

Abstract: A target image of a target circuit board and a gold image of a gold circuit board are taken by an image acquisition system. Fiducial points are located on the target image and on the gold image. Perspective transformation is performed on the target image using the fiducial points on the target image for reference and on the gold image using the fiducial points on the gold image for reference. After perspective transformation, an anomalous section of the target image is identified by identifying pixels that have different intensities between the target image and the gold image, the anomalous section being indicative of an unauthorized modification to the target circuit board.

Abstract: The present invention relates to controlled release formulations for treating hearing loss and a method for preparing the same, and more particularly, to controlled release formulations for treating hearing loss prepared by dispersing a steroidal anti-inflammatory agent encapsulated in low molecular weight hyaluronic acid in an aqueous solution of high molecular weight hyaluronic acid and a method for preparing the same.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: A memory system may include a memory device including at least one sequential area in which a data corresponding to consecutive logical addresses of the at least one sequential area is stored, a sequential buffer configured to temporarily store the data to be stored in the at least one sequential area, a meta buffer configured to store a meta data including a write pointer information indicating a logical address in which data is to be stored from among logical addresses corresponding to the at least one sequential area, and an area state information indicating whether the sequential buffer is allocated to the at least one sequential area, and a memory controller configured to perform a write operation of storing the data in the at least one sequential area in response to a first command received from the host using the meta data.