Abstract: A method for joining together metal workpiece (12,14 or 12,150, 14) includes forming a laser weld joint (66) in a workpiece stack-up (10) that fusion welds two or more overlapping metal workpiece (12,14 or 12,150 or 14) together. The laser weld joint (66) has an initial top surface (76). Once the laser weld joint (66) is formed, the method calls for impinging the laser weld joint (66) with a laser beam (24) and moving the laser beam (24) along the initial joint (66) including the initial top surface (76). The laser beam (24) is eventually removed from the laser weld joint (66) to allow the melted upper portion (78) of the joint (66) to resolidify and provide the laser weld joint (66) with a modified top surface (84) that is smoother than the initial top surface (76). By providing the laser weld joint with a smoother modified top surface, residual stress concentration points are removed and the laser weld joint is less liable to damage seal strips.

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Abstract: An aspect of the present invention discloses a method for extracting content from a document. The method includes one or more processors identifying a visual anchor corresponding to a text element depicted in a first document utilizing an edge detection analysis. The method further includes determining edge coordinates of the text element depicted in the first document. The method further includes determining text at a leading edge of the text element depicted in the first document and text at a trailing edge of the text element depicted in the first document, based on the determined edge coordinates. The method further includes extracting a complete version of the text element depicted in the first document, from a plain text version of the first document, utilizing the determined text at the leading edge of the text element and the determined text at the trailing edge of the text element.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

Abstract: A spiky metal organic framework is provided in the present disclosure. The spiky metal organic framework is formed by a coordination reaction between at least one metal ion and an organic ligand, and includes a body and a plurality of spike-like structures. The body is a spherical shape, and a particle size of the body is 1 ?m to 3 ?m. The spike-like structures are distributed on a surface of the body, a diameter of each spike-like structure is 15 nm to 35 nm, and a length of each spike-like structure is 250 nm to 400 nm.

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Abstract: A negative pressure protection system has a cover enclosing an inner space, a ventilation duct fluidly communicating with an air outlet port of the cover, a filter having an inlet end communicating with the ventilation duct, and an air exhausting device connected to an outlet end of the filter. The air exhausting device draws air out from the inner space of the cover via the ventilation duct. The air is filtered and purified by the filter and then is exhausted away by the exhausting device.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.

Abstract: Among other things, techniques are described for obtaining a range image related to a depth sensor of a vehicle operating in an environment. A first data point is identified in the range image with an intensity at or below a first intensity threshold. A first number of data points are determined in the range image that have an intensity at or above a second intensity threshold in a first region of the range image. Then, it is determined whether the first number of data points is at or above a region number threshold. The first data point is removed from the range image if the first number of data points is at or above the region number threshold. Operation of the vehicle is then facilitated in the environment based at least in part on the range image. Other embodiments may be described or claimed.

Abstract: A computing in-memory system and computing in-memory method based on a skyrmion race memory are provided. The system comprises a circuit architecture of SRM-CIM. The circuit architecture of the SRM-CIM comprises a row decoder, a column decoder, a voltage-driven, a storage array, a modified sensor circuit, a counter Bit-counter and a mode controller. The voltage-driven includes two NMOSs, and the two NMOSs are respectively connected with a selector MUX. The modified sensor circuit compares the resistance between a first node to a second node and a third node to a fourth node by using a pre-charge sense amplifier. The storage array is composed of the skyrmion racetrack memories. The computing in-memory architecture is designed by utilizing the skyrmion racetrack memory, so that storage is realized in the memory, and computing operation can be carried out in the memory.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

Abstract: A method of treating a subject suffering from cancer comprising a step of administering an effective amount of a group of double-stranded RNA molecules to the subject, wherein the RNA molecule is isolated or derived from a bacteria of the genus Escherichia. A method of inhibiting growth or proliferation of cancer cells comprising a step of contacting said cells with said RNA molecule; and a pharmaceutical composition for treating cancer comprising said RNA molecule and a pharmaceutically tolerable excipient. Also a double-stranded RNA molecule and a recombinant vector comprising the double-stranded RNA molecule.

Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.