Abstract: Provided are methods for predicting motion of hypothetical agents, which can include receiving sensor data, generating a segmentation mask indicative of at least one occluded area, generating at least one hypothetical agent trajectory, determining at least one agent generation point, determining whether a threshold distance from the at least one agent generation point to the vehicle is satisfied, generating at least one agent, planning a path of the vehicle and controlling the vehicle according to the planned path. Systems and computer program products are also provided.

Abstract: Embodiments provide enhanced performance diagnosis in a network computing environment. In response to an occurrence of a performance issue for a node while under operating conditions, common logs for applications on the node are analyzed. The applications are respectively registered in advance for diagnosis services. The applications each register rules in advance for the diagnosis services. At a time of the performance issue, debug programs are automatically issued to generate debug level logs respectively for the applications. Debug level logs are analyzed according to the rules to determine a root cause of the performance issue. A potential solution to the root cause of the performance issue is determined using the rules, without having to recreate the operating conditions occurring during the performance issue. The potential solution to rectify the root cause of the performance issue is executed without having to recreate the operating conditions occurring during the performance issue.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: obtaining pre-check data associated with specified data nodes; calculating outliers for each specified data node, wherein the outliers are calculated based on a unit of the pre-check data associated with each specified data node; backtracking the calculated outliers for each specified data node through an associated generating data link; selecting one or more data nodes associated with a set of largest outliers; selecting one or more data links associated with the set of largest outliers; and generating potential anomaly indications based on the one or more data nodes selected and the one or more data links selected.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

Abstract: Presented are systems and methods for configuring component carrier groups. A wireless communication device may determine a first reference signal associated with a second reference signal. The wireless communication device may determine information of a target signal in a first component carrier (CC) according to the first reference signal. The second reference signal may be in a second CC in an activated beam state.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. Embodiments herein relate to an operational envelope detector that is configured to receive, as inputs, information related to sensors of the system and information related to operational design domain (ODD) requirements. The OED then compares the information related to sensors of the system to the information related to the ODD requirements, and identifies whether the system is operating within its ODD or whether a remedial action is appropriate to adjust the ODD requirements based on the current sensor information. Other embodiments are described and/or claimed.

Abstract: Among other things, techniques are described for spatially and temporally consistent ground modelling with information fusion. A vehicle location and orientation is obtained and an instantaneous ground height estimation is obtained for anchor cells of a grid map of the vehicle based on the obtained vehicle location and orientation. A pseudo ground height associated with non-anchor cells of the grid map is computed. A Bayesian filtering framework is used to generate a final ground height estimate for the anchor cells and the non-anchor cells based on the instantaneous ground height estimation for the anchor cells, the pseudo ground height associated with non-anchor cells, an estimated ground height from a previous timestamp, or any combinations thereof. The vehicle operates according to the final ground height estimate.

Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. Embodiments herein relate to an operational envelope detector that is configured to receive, as inputs, information related to sensors of the system and information related to operational design domain (ODD) requirements. The OED then compares the information related to sensors of the system to the information related to the ODD requirements, and identifies whether the system is operating within its ODD or whether a remedial action is appropriate to adjust the ODD requirements based on the current sensor information. Other embodiments are described and/or claimed.

Abstract: Provided are an information determination method and device, a receiving method and device, a communication node, and a medium. The method includes: receiving indication information; and determining channel state information of M physical uplink channel transmissions according to the indication information, where M is an integer greater than or equal to 1.

Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. Embodiments herein relate to an operational envelope detector that is configured to receive, as inputs, information related to sensors of the system and information related to operational design domain (ODD) requirements. The OED then compares the information related to sensors of the system to the information related to the ODD requirements, and identifies whether the system is operating within its ODD or whether a remedial action is appropriate to adjust the ODD requirements based on the current sensor information. Other embodiments are described and/or claimed.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an image having characters that correspond to a language, and using a text recognition algorithm to determine a first language believed to correspond to the characters. A first confidence level associated with the first language is also computed, and a determination is made as to whether the first confidence level associated with the first language is outside a predetermined range. In response to determining that the first confidence level associated with the first language is not outside the predetermined range, the first language is output as the given language. The text recognition algorithm is trained using a simple shallow neural network and a generated mixed language corpus. The generated mixed language corpus is formed by: randomly sampling libraries having vocabulary and/or characters therein, and combining the randomly sampled vocabulary and/or characters to form the generated mixed language corpus.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: A system and method for wireless communication are disclosed herein. Example implementations includes a wireless communication method of receiving a first control information and a second control information, wherein the first control information comprises a first format, and the second control information comprises a second format, and determining that the second control information is a repeat of the first control information based at least in part on the first format and the second format. Example implementations further include a method where each of the first control information and the second control information is Downlink Control Information (DCI), the first control information comprises a first field containing a first index, the first control information comprises a second field containing a second index, and the field is scrambled by a network identifier.

Abstract: Chucks for supporting semiconductor wafers during certain processing operations are disclosed. The chucks may include a recessed region near the outer perimeter of the wafer that has one or more surfaces that face towards the wafer but are recessed therefrom so as to not contact the wafer around the perimeter of the wafer. The use of such a recessed region prevents direct thermally conductive contact between the chuck and the wafer, thereby allowing the wafer to achieve a more uniform temperature distribution in certain process conditions. This has the further effect of causing certain processing operations to be more uniform with respect to edge-center deposition (or etch) layer thickness.

Abstract: Embodiments provide enhanced performance diagnosis in a network computing environment. In response to an occurrence of a performance issue for a node while under operating conditions, common logs for applications on the node are analyzed. The applications are respectively registered in advance for diagnosis services. The applications each register rules in advance for the diagnosis services. At a time of the performance issue, debug programs are automatically issued to generate debug level logs respectively for the applications. Debug level logs are analyzed according to the rules to determine a root cause of the performance issue. A potential solution to the root cause of the performance issue is determined using the rules, without having to recreate the operating conditions occurring during the performance issue. The potential solution to rectify the root cause of the performance issue is executed without having to recreate the operating conditions occurring during the performance issue.

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.