Abstract: Prompt learning is performed, using a prompt encoder, on an input data set to generate a revised text pattern. The revised text pattern is processed, using a text generative adversarial network, based on an existing data set to generate a fused data set and a machine learning system is updated with the fused data set.

Abstract: An automatic real-time basketball box score recording and analysis system with videos captured from arbitrary angles is applied to a basketball game. A shot analyzing step is performed to analyze the videos to determine whether one of the videos is a real shot event to generate a shot analysis result. A data calculating step is performed to analyze the videos to determine that the real shot event is a three-point shot, a two-point shot or a free throw to generate a scoring result, and then calculate a game data according to the shot analysis result and the scoring result. A player analyzing step is performed to analyze the videos to obtain a posture analysis data of a shooter. The posture analysis data is configured to evaluate a performance of the shooter when shooting. An interface device is configured to modify and display the game data.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.

Abstract: A cleaning system and a base station. In a working process, an airflow is generated by a drawer, to draw garbage on the ground on a traveling path into a dust box. Before the airflow entering the dust box is discharged outside a cleaning robot, the airflow flows through an air filter, and dust carried by the airflow is filtered out under a filtering function of the air filter. When dust accumulation in the air filter needs to be cleaned or the dust box needs to be emptied, the air filter is driven by a dust cleaner to vibrate, so as to shake off dust in the air filter, and the garbage in the dust box is collected by using a collector of the base station.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

Abstract: Systems and methods for indicating positioning information in wireless communication systems are disclosed. In one aspect, the method includes determining, by a wireless communication device, transmission Timing Error Group (TEG) information of the wireless communication device according to at least one of usage of Sounding Reference Signal (SRS) transmission, UE antenna coherent capability, UE antenna switching capability, or SRS port. The transmission TEG information includes at least one of a number of transmission TEGs, an association between the transmission TEGs and SRS transmission. The SRS transmission includes at least one of a SRS resource set, a SRS resource, or a SRS port. The method also includes communicating, by the wireless communication device with a network, using the transmission TEG information.

Abstract: The present invention relates to a silk fibroin/hydroxyapatite composite material, and a preparation method therefor and an application thereof. A uniform mixture of hydroxyapatite nanoparticles, silk fibroin, and hexafluoroisopropanol is maintained at a temperature range from 50° C. to 60° C. for at least 1 hour to obtain a silk fibroin/hydroxyapatite solution; the silk fibroin/hydroxyapatite solution is poured into a long cylindrical mold, two ends of the long cylindrical mold being respectively an end A and an end B; at room temperature, the end A is opened and the end B is closed, and the mold is vertically immersed in methanol with the opening facing up and let stand for at least 2 days; the mold is turned upside down, the end A is closed and the end B is opened, and the mold is vertically immersed in the methanol with the opening facing up and let stand for at least 2 days; the mold is removed, and ventilation and drying are performed to obtain a silk fibroin/hydroxyapatite composite material.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving an image having characters that correspond to a language, and using a text recognition algorithm to determine a first language believed to correspond to the characters. A first confidence level associated with the first language is also computed, and a determination is made as to whether the first confidence level associated with the first language is outside a predetermined range. In response to determining that the first confidence level associated with the first language is not outside the predetermined range, the first language is output as the given language. The text recognition algorithm is trained using a simple shallow neural network and a generated mixed language corpus. The generated mixed language corpus is formed by: randomly sampling libraries having vocabulary and/or characters therein, and combining the randomly sampled vocabulary and/or characters to form the generated mixed language corpus.

Abstract: A wireless communication method includes requesting, by a wireless communication entity, user equipment (UE) to provide location information; and providing, by the wireless communication entity, a measurement gap to a wireless communication node or the UE.

Abstract: Among other things, techniques are described for determining precedence order at a multiway stop. In embodiments, identifications are assigned to tracks, and young tracks are compared to stale tracks. A young track matches a stale track based on one or more factors. An identification of the young track is reassigned to an identification of the stale track, wherein the young track is determined to match the stale track based on the one or more factors. An earliest time of appearance of agents is determined based on identifications and in view of perception obscured areas. A precedence order for navigating through the intersection is determined based on local rules, the identifications, and the earliest time of appearance of agents, and the vehicle proceeds through the multiway stop intersection in accordance with the precedence order.

Abstract: Presented are systems, methods, apparatuses, or computer-readable media for configuring reference signaling. A wireless communication device may determine a set of resources. A number of resources in the set may be equal to or more than one and the set satisfies a character. Each of the resources may be associated with a respective value of information.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: Methods and apparatuses are described that provide tungsten deposition with low roughness. In some embodiments, the methods involve co-flowing nitrogen with hydrogen during an atomic layer deposition process of depositing tungsten that uses hydrogen as a reducing agent. In some embodiments, the methods involve depositing a cap layer, such as tungsten oxide or amorphous tungsten layer, on a sidewall surface of a 3D NAND structure. The disclosed embodiments have a wide variety of applications including depositing tungsten into 3D NAND structures.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.