Abstract: A computer-implemented method, according to one embodiment, includes: receiving an image having characters that correspond to a language, and using a text recognition algorithm to determine a first language believed to correspond to the characters. A first confidence level associated with the first language is also computed, and a determination is made as to whether the first confidence level associated with the first language is outside a predetermined range. In response to determining that the first confidence level associated with the first language is not outside the predetermined range, the first language is output as the given language. The text recognition algorithm is trained using a simple shallow neural network and a generated mixed language corpus. The generated mixed language corpus is formed by: randomly sampling libraries having vocabulary and/or characters therein, and combining the randomly sampled vocabulary and/or characters to form the generated mixed language corpus.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

Abstract: A system and method for wireless communication are disclosed herein. Example implementations includes a wireless communication method of receiving a first control information and a second control information, wherein the first control information comprises a first format, and the second control information comprises a second format, and determining that the second control information is a repeat of the first control information based at least in part on the first format and the second format. Example implementations further include a method where each of the first control information and the second control information is Downlink Control Information (DCI), the first control information comprises a first field containing a first index, the first control information comprises a second field containing a second index, and the field is scrambled by a network identifier.

Abstract: Chucks for supporting semiconductor wafers during certain processing operations are disclosed. The chucks may include a recessed region near the outer perimeter of the wafer that has one or more surfaces that face towards the wafer but are recessed therefrom so as to not contact the wafer around the perimeter of the wafer. The use of such a recessed region prevents direct thermally conductive contact between the chuck and the wafer, thereby allowing the wafer to achieve a more uniform temperature distribution in certain process conditions. This has the further effect of causing certain processing operations to be more uniform with respect to edge-center deposition (or etch) layer thickness.

Abstract: Embodiments provide enhanced performance diagnosis in a network computing environment. In response to an occurrence of a performance issue for a node while under operating conditions, common logs for applications on the node are analyzed. The applications are respectively registered in advance for diagnosis services. The applications each register rules in advance for the diagnosis services. At a time of the performance issue, debug programs are automatically issued to generate debug level logs respectively for the applications. Debug level logs are analyzed according to the rules to determine a root cause of the performance issue. A potential solution to the root cause of the performance issue is determined using the rules, without having to recreate the operating conditions occurring during the performance issue. The potential solution to rectify the root cause of the performance issue is executed without having to recreate the operating conditions occurring during the performance issue.

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Abstract: A method, computer system, and a computer program product for optical character recognition training are provided. A text image and plain text labels for the text image may be received. The text image may include words. The plain text labels may include machine-encoded text corresponding to the words. Semantic feature vectors for the words, respectively, may be generated based on the plain text label. The text image, the plain text labels, and the semantic feature vectors may be input together into a machine learning model to train the machine learning model for optical character recognition. The plain text labels and the semantic feature vectors may be constraints for the training.

Abstract: Reducing an average give-away rate of a weighing device by determining a weight of a product of a weighing device that includes an article, determining one or more conditions of an environment of the weighing device, determining a state of the environment of the weighing device, wherein the state relates to an average give-away rate of the environment of the weighing device, determining a reward value for the state of the environment of the weighing device, wherein the reward value is based at least in part on the weight of the product, and generating a set of parameters for the weighing device based at least in part on the environment, the state, and the reward.

Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A wireless communication method is described. The method is performed by a user device and comprises: determining a list of one or more reference signals; receiving, during a first time unit, a first signaling that includes a state; determining a relationship between a reference signal corresponding to the state and the list; and determining, based on the relationship, a second time unit associated with the state or the first signaling.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: Information determination, acquisition and transmission methods, apparatuses and devices, and a storage medium are provided. The information determination method includes: acquiring a target parameter according to a downlink information element and second information, wherein the second information includes at least one of: timing advance information, a predetermined parameter, a number of repeated transmissions of an uplink target information element, a time-domain behavior parameter of the uplink target information element, a predetermined Component Carrier (CC) group, and a correspondence relationship between the downlink information element and an uplink target information element, and the target parameter is spatial transmitting filter information of an uplink target information element.

Abstract: In an approach for a text block recognition in a document, a processor detects characters in the document using an object detection technique. A processor identifies positions of the detected characters in the document. A processor analyzes semantic connectivity among the detected characters based on the positions and semantic connectivity of the characters. A processor recognizes text blocks of related characters based on the semantic connectivity analysis. A processor outputs the text blocks associated with the related characters.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: Presented are systems, methods, apparatuses, or computer-readable media for performing positioning procedures. A wireless communication device may receive, from a wireless communication node, information to facilitate positioning of the wireless communication device. The wireless communication device may determine to initiate a positioning procedure while in radio resource control (RRC) inactive state. The wireless communication device may perform, while in RRC inactive state, the positioning procedure.

Abstract: Presented are systems, methods, apparatuses, or computer-readable media for positioning using multiple frequency layers. A first communication device may configure a first aggregated positioning information for aggregated positioning measurement in a first plurality of frequency layers. The first communication device may receive, from the second communication device, a report comprising a second aggregated positioning information for aggregated positioning measurement in a second plurality of frequency layers. The first aggregated positioning information may be associated with at least one of the first plurality of frequency layers, and the second aggregated positioning information may be associated with at least one of the second plurality of frequency layers.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.