Patents by Inventor Yu Ping

Yu Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210399209
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210390993
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210391531
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.
    Type: Application
    Filed: July 15, 2020
    Publication date: December 16, 2021
    Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210389394
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
    Type: Application
    Filed: July 13, 2020
    Publication date: December 16, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Method for fabricating semiconductor device including embedded magnetic resistance random access memory
    Patent number: 11195994
    Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Chen-Yi Weng, Si-Han Tsai, Jing-Yin Jhang, Yu-Ping Wang
  • MATERIALS AND METHODS FOR DETECTING CORONAVIRUS
    Publication number: 20210340635
    Abstract: The disclosure relates to test kits and methods for detecting the presence of Coronavirus polynucleotides in a biological sample.
    Type: Application
    Filed: June 19, 2020
    Publication date: November 4, 2021
    Inventors: Sylvia Daunert, Sapna K. Deo, Jean-Marc Zingg, Emre Dikici, Yu-Ping Yang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210343935
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
    Type: Application
    Filed: May 27, 2020
    Publication date: November 4, 2021
    Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210343786
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Application
    Filed: May 26, 2020
    Publication date: November 4, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Content item forking and merging
    Patent number: 11161045
    Abstract: Techniques for forking and merging of electronically presented content items, such as MMO and other video games, are described herein. In particular, a first content item session may be forked to generate a second (forked) content item session. The first and forked content item sessions may then continue to execute and evolve in separate directions from one another. In some examples, a user of the forked content item session may serve as an administrator of the forked content item session and may receive compensation in exchange for serving as an administrator. Additionally, one or more forked or other separate content item sessions may be merged together to form a merged content item session. In some examples, conflicts between merged content item sessions may be identified and resolved based, at least in part, on input from administrators.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 2, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Francis Xavier Surjo-Subagio, Brian David Fisher, David Edward Maldonado, Patrick Gilmore, Christopher Thomas Larson, Yu Ping Hu
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210328133
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.
    Type: Application
    Filed: May 12, 2020
    Publication date: October 21, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Adaptive self-centering apparatus and method for seismic and wind protection of structures
    Patent number: 11136778
    Abstract: An adaptive self-centering device (ASCD) which uses one or more ratchet-pawl mechanisms. The hysteretic slip force of the ASCD preferably comes from a friction mechanism. The self-centering originates from the ratcheting of the pawl over the ratchet wheel and a self-centering device, in response to a force from an apparatus such as a spring. The nonlinear hardening of the apparatus, which conforms to the favorable adaptive behavior sought in modern day passive devices, stems from the mechanism of the lever within the apparatus that transforms the linear motion into rotatory motion.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 5, 2021
    Assignee: Arrowhead Center, Inc.
    Inventors: Tathagata Ray, Yu-Ping Tang, Charles Park
  • Semiconductor structure and method for forming the same
    Patent number: 11139011
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Magnetoresistive random access memory
    Patent number: 11139428
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210305316
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.
    Type: Application
    Filed: April 23, 2020
    Publication date: September 30, 2021
    Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210296572
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210296570
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • SYSTEMS AND METHODS FOR DETECTING A MOTOR DEVELOPMENTAL DELAY OR NEURODEVELOPMENTAL DISORDER IN AN INFANT
    Publication number: 20210267492
    Abstract: Systems and methods for detecting a motor developmental delay and/or neurodevelopmental disorder of an infant are described herein. An example method can include receiving motion data associated with the infant's gross motor activity; analyzing, using a machine learning algorithm, the motion data to detect a kinematic feature; comparing the kinematic feature to an expected relationship between the kinematic feature and infant age; and detecting the neurodevelopmental disorder based on the comparison. An infant sensor suit is also described herein. An example infant sensor suit can include an article of clothing; a plurality of sensors; a power source operably coupled to the sensors; and a wireless transmitter operably coupled to the sensors. The sensors, power source, and wireless transmitter can be incorporated into the article of clothing.
    Type: Application
    Filed: July 19, 2019
    Publication date: September 2, 2021
    Inventors: Katelyn Elizabeth FRY, Faraz Muhammad YOUSUF, Yu-Ping CHEN, Ayanna Howard
  • REDISTRIBUTION LAYER OF FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210272907
    Abstract: A redistribution layer of fan-out package and manufacturing method thereof is disclosed. Before forming a pattern wiring layer on each dielectric insulation layer, a thin metal ion layer is formed firstly. A connection between the metal ion layer and the corresponding dielectric insulation layer is weaker than that between the patterned wiring layer and the corresponding dielectric insulation layer. When the redistribution layer is placed in a high temperature and high humidity environment, the stress generated by the patterned circuit layer causes that multiple gaps to form between the metal ion layers and the corresponding dielectric insulating layer. Therefore, a distance between the adjacent dielectric insulating layer and the patterned wiring layer is increased to reduce the capacitive effect and the power consumption of the thinner redistribution layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 2, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Yi WANG, Yu-Ping WANG
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210257542
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • METHOD AND APPARATUS FOR CLEANING PROCESS MONITORING
    Publication number: 20210252668
    Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Charlie WANG, Yu-Ping TSENG, Y.J. CHEN, Wai-Ming YEUNG, Chien-Shen CHEN, Danny KUO, Yu-Hsuan HSIEH, Hsuan LO