Patents by Inventor Yu Ping

Yu Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230157182
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, Rai-Min Huang, Ya-Huei Tsai, I-Fan Chang, Yu-Ping Wang
  • Patent number: 11646069
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 9, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 11646353
    Abstract: A semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a first well region, and a first structure. The substrate has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is in the substrate and between the first gate structure and the second gate structure. The first structure is disposed in the first well region. A shape of the first structure has an acute angle.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: May 9, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Ping Chen, Chun-Shun Huang
  • Patent number: 11637233
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Grant
    Filed: November 1, 2020
    Date of Patent: April 25, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11634723
    Abstract: The present invention is directed to promoter sequences and promoter control elements, polynucleotide constructs comprising the promoters and control elements, and methods of identifying the promoters, control elements, or fragments thereof. The invention further relates to the use of the present promoters or promoter control elements to modulate transcript levels.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: April 25, 2023
    Assignee: Ceres, Inc.
    Inventors: Zhihong Cook, Yiwen Fang, Kenneth A. Feldmann, Edward Kiegle, Shing Kwok, Yu-Ping Lu, Leonard Medrano, Roger Pennell, Richard Schneeberger, Chuan-Yin Wu, Nestor Apuya, Jack K. Okamuro, Diane K. Jofuku, Jonathan Donson, David Van-Dinh Dang, Emilio Margolles-Clark, Nickolai Alexandrov, Tatiana Tatarinova, Noah Theiss, Danielle Grizard, Shawna Davis, Dennis Robles, Michael Portereiko
  • Patent number: 11624949
    Abstract: A display device including a display area and a non-display area is provided. The display area includes a display panel, a switch unit and a first reflective film. The non-display area includes a second reflective film. The switch unit is disposed on the display panel. The first reflective film is disposed between the display panel and the switch unit. When the display device is set in a pattern mode, the display panel does not emit image light. For the pattern mode, the reflectivity in the display area is approximately equal to the reflectivity in the non-display area for ambient light.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 11, 2023
    Assignee: Au Optronics Corporation
    Inventors: Chia-Chun Hsu, Yu-Ping Kuo, Hsiao-Wei Cheng
  • Publication number: 20230106156
    Abstract: A semiconductor device includes a first metal interconnection on a substrate, a first inter-metal dielectric (IMD) layer around the first metal interconnection, an electromigration enhancing layer on the first metal interconnection, a second IMD layer on and around the electromigration enhancing layer, and a second metal interconnection on the electromigration enhancing layer.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 6, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20230097481
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.
    Type: Application
    Filed: November 3, 2021
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Publication number: 20230101233
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 11616193
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 28, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11611035
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: March 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20230084241
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
  • Publication number: 20230066690
    Abstract: A display device including a display area and a non-display area is provided. The display area includes a display panel, a switch unit and a first reflective film. The non-display area includes a second reflective film. The switch unit is disposed on the display panel. The first reflective film is disposed between the display panel and the switch unit. When the display device is set in a pattern mode, the display panel does not emit image light. For the pattern mode, the reflectivity in the display area is approximately equal to the reflectivity in the non-display area for ambient light.
    Type: Application
    Filed: October 29, 2021
    Publication date: March 2, 2023
    Applicant: Au Optronics Corporation
    Inventors: Chia-Chun Hsu, Yu-Ping Kuo, Hsiao-Wei Cheng
  • Patent number: 11583848
    Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 21, 2023
    Assignee: CHANG GUNG UNIVERSITY
    Inventors: Chia-Ming Yang, Chao-Sung Lai, Yu-Ping Chen, Min-Hsien Wu
  • Publication number: 20230051398
    Abstract: Described herein is a method for detecting the presence of circulating extracellular vesicles in a subject. The method comprises contacting a biological sample from the subject with an antibody mimetic that specifically binds to a cell surface marker on the vesicles, wherein the antibody mimetic is coupled to a detectable label; and detecting presence of extracellular vesicles in the sample by detecting the presence of the detectable label coupled to the antibody mimetic bound to the vesicles.
    Type: Application
    Filed: December 11, 2020
    Publication date: February 16, 2023
    Inventors: Sylvia Daunert, Yu-Ping Yang
  • Publication number: 20230038528
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Application
    Filed: October 18, 2022
    Publication date: February 9, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20230013337
    Abstract: A window blind includes a headrail, two lift cords, a blind body, a bottom rail, and two cord winding assemblies that are respectively installed on two opposite sides of the long axis of the bottom rail. The other ends of the lift cords are respectively tied to respective adjustment columns of the cord winding assemblies. When the window blind is folded or stretched, unfortunately, when the winding stroke is inconsistent, the blind body is not folded uniformly or skewed, and the adjustment column of the cord winding assembly on one side can be finely adjusted, so that one of the lift cords is gradually wound and covered on the adjustment column, and indirectly drives the bottom rail and the blind body to gradually adjust to substantially parallel to the bottom of the headrail, thereby effectively achieving the effect of fine-tuning and correcting the blind body.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 19, 2023
    Applicant: CHING FENG HOME FASHIONS CO., LTD.
    Inventors: MING-CHU CHIANG, YU-PING CHOU
  • Publication number: 20230020200
    Abstract: The disclosure provides an Internet of things device and a battery power supply circuit thereof. A voltage of a battery is compared with a predetermined over-discharge voltage to generate a comparison signal. A battery protection circuit serves as a power supply path from the battery to a load and determines whether to cut off the power supply path according to the comparison signal. The battery protection circuit cuts off the power supply path when the voltage of the battery decreases from a value greater than the predetermined over-discharge voltage to a value less than the predetermined over-discharge voltage, but does not turn on the power supply path when the voltage of the battery increases from a value less than the predetermined over-discharge voltage to a value greater than the predetermined over-discharge voltage.
    Type: Application
    Filed: March 23, 2022
    Publication date: January 19, 2023
    Applicant: Sercomm Corporation
    Inventors: Meng-Chien Chiang, Yu Ping Hsu
  • Patent number: 11552241
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 10, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20230001040
    Abstract: An air sterilizing device has a casing, a wheel disc covered with microporous structures, a blower, and a sterilizing module. The casing has an air inlet and an air outlet. The blower located in the casing introduces the external air from the air inlet, and the external air is filtered and sterilized by the wheel disc and the sterilizing module. The filtered and sterilized air is discharged from the air outlet. The sterilizing module locates next to the wheel disc for sterilizing the air flowing through the sterilizing module and also for sterilizing the wheel disc by the relative rotation between the wheel disc and the sterilizing module. Bacteria and viruses attached to the wheel disc are eliminated, and the filtration and sterilization functions of the wheel disc are maintained. The efficacy and the efficiency of the air sterilizing device are therefore improved.
    Type: Application
    Filed: April 19, 2022
    Publication date: January 5, 2023
    Applicant: Norm Pacific Automation Corp.
    Inventors: Horng-Tsann Huang, Yu-Ping Wang, I-Chieh Chen