Patents by Inventor Yu Ping

Yu Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive self-centering apparatus and method for seismic and wind protection of structures
    Patent number: 11136778
    Abstract: An adaptive self-centering device (ASCD) which uses one or more ratchet-pawl mechanisms. The hysteretic slip force of the ASCD preferably comes from a friction mechanism. The self-centering originates from the ratcheting of the pawl over the ratchet wheel and a self-centering device, in response to a force from an apparatus such as a spring. The nonlinear hardening of the apparatus, which conforms to the favorable adaptive behavior sought in modern day passive devices, stems from the mechanism of the lever within the apparatus that transforms the linear motion into rotatory motion.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 5, 2021
    Assignee: Arrowhead Center, Inc.
    Inventors: Tathagata Ray, Yu-Ping Tang, Charles Park
  • Magnetoresistive random access memory
    Patent number: 11139428
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Semiconductor structure and method for forming the same
    Patent number: 11139011
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210305316
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.
    Type: Application
    Filed: April 23, 2020
    Publication date: September 30, 2021
    Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210296572
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210296570
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • SYSTEMS AND METHODS FOR DETECTING A MOTOR DEVELOPMENTAL DELAY OR NEURODEVELOPMENTAL DISORDER IN AN INFANT
    Publication number: 20210267492
    Abstract: Systems and methods for detecting a motor developmental delay and/or neurodevelopmental disorder of an infant are described herein. An example method can include receiving motion data associated with the infant's gross motor activity; analyzing, using a machine learning algorithm, the motion data to detect a kinematic feature; comparing the kinematic feature to an expected relationship between the kinematic feature and infant age; and detecting the neurodevelopmental disorder based on the comparison. An infant sensor suit is also described herein. An example infant sensor suit can include an article of clothing; a plurality of sensors; a power source operably coupled to the sensors; and a wireless transmitter operably coupled to the sensors. The sensors, power source, and wireless transmitter can be incorporated into the article of clothing.
    Type: Application
    Filed: July 19, 2019
    Publication date: September 2, 2021
    Inventors: Katelyn Elizabeth FRY, Faraz Muhammad YOUSUF, Yu-Ping CHEN, Ayanna Howard
  • REDISTRIBUTION LAYER OF FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210272907
    Abstract: A redistribution layer of fan-out package and manufacturing method thereof is disclosed. Before forming a pattern wiring layer on each dielectric insulation layer, a thin metal ion layer is formed firstly. A connection between the metal ion layer and the corresponding dielectric insulation layer is weaker than that between the patterned wiring layer and the corresponding dielectric insulation layer. When the redistribution layer is placed in a high temperature and high humidity environment, the stress generated by the patterned circuit layer causes that multiple gaps to form between the metal ion layers and the corresponding dielectric insulating layer. Therefore, a distance between the adjacent dielectric insulating layer and the patterned wiring layer is increased to reduce the capacitive effect and the power consumption of the thinner redistribution layer.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 2, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Yi WANG, Yu-Ping WANG
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210257542
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • METHOD AND APPARATUS FOR CLEANING PROCESS MONITORING
    Publication number: 20210252668
    Abstract: A cleaning process monitoring system, comprising: a cleaning container comprising an inlet for receiving a cleaning solution and an outlet for draining a waste solution; a particle detector coupled to the outlet and configured to measure a plurality of particle parameters associated with the waste solution so as to provide a real-time monitoring of the cleaning process; a pump coupled to the cleaning container and configured to provide suction force to draw solution through the cleaning system; a controller coupled to the pump and the particle detector and configured to receive the plurality of particle parameters from the particle detector and to provide control to the cleaning system; and a host computer coupled to the controller and configured to provide at least one control parameter to the controller.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Charlie WANG, Yu-Ping TSENG, Y.J. CHEN, Wai-Ming YEUNG, Chien-Shen CHEN, Danny KUO, Yu-Hsuan HSIEH, Hsuan LO
  • Magnetoresistive random-access memory
    Patent number: 11087812
    Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Hui Lee, I-Ming Tseng, Chiu-Jung Chiu, Chung-Liang Chu, Yu-Chun Chen, Ya-Sheng Feng, Yi-An Shih, Hsiu-Hao Hu, Yu-Ping Wang
  • Non-volatile memory and memory sector thereof
    Patent number: 11074963
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210225933
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.
    Type: Application
    Filed: February 16, 2020
    Publication date: July 22, 2021
    Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210226119
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • METHOD AND DEVICE FOR RIGHT-LEFT DISCRIMINATION OF A GAIT TRAJECTORY
    Publication number: 20210223282
    Abstract: A method for right-left discrimination of a gait trajectory includes: a) obtaining a gait trajectory of a motion sensor based on motion information outputted by the motion sensor, where the motion sensor is mounted on one of left and right shoes, the motion information contains plural sets of coordinates representing positions of the one of left and right shoes, and the gait trajectory is constituted by the plural sets of coordinates; and b) calculating a slope of at least one line each between corresponding adjacent two sets of coordinates among the plural sets of coordinates, determining that the motion sensor is mounted on the right shoe When the slope is greater than zero, and determining that the motion sensor is mounted on the left shoe when the slope is smaller than zero.
    Type: Application
    Filed: February 26, 2020
    Publication date: July 22, 2021
    Inventor: Yu-Ping TSENG
  • MRAM STRUCTURE
    Publication number: 20210225414
    Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: Po-Kai Hsu, Hung-Yueh Chen, Kun-I Chou, Jing-Yin Jhang, Hui-Lin Wang, Yu-Ping Wang
  • Semiconductor device and method for fabricating the same
    Patent number: 11063207
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Semiconductor device and method for fabricating the same
    Patent number: 11063206
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210184104
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 17, 2021
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210167281
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
    Type: Application
    Filed: January 2, 2020
    Publication date: June 3, 2021
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang