Patents by Inventor Yu Ping

Yu Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11739340
    Abstract: The present invention is directed to promoter sequences and promoter control elements, polynucleotide constructs comprising the promoters and control elements, and methods of identifying the promoters, control elements, or fragments thereof. The invention further relates to the use of the present promoters or promoter control elements to modulate transcript levels.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 29, 2023
    Assignee: Ceres, Inc.
    Inventors: Zhihong Cook, Yiwen Fang, Kenneth A. Feldmann, Edward Kiegle, Shing Kwok, Yu-Ping Lu, Leonard Medrano, Roger Pennell, Richard Schneeberger, Chuan-Yin Wu, Nestor Apuya, Jack K. Okamuro, Diane K. Jofuku, Jonathan Donson, David Van-Dinh Dang, Emilio Margolles-Clark, Nickolai Alexandrov, Tatiana Tatarinova, Noah Theiss, Danielle Grizard, Shawna Davis, Dennis Robles, Michael Portereiko
  • Patent number: 11744160
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: August 29, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yu-Ping Wang
  • Publication number: 20230263067
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 17, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 11721759
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: August 8, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Ping Chen, Jhen-Yu Tsai
  • Publication number: 20230247915
    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
  • Publication number: 20230247914
    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 11716860
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 11715499
    Abstract: A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hung-Yueh Chen, Kun-I Chou, Jing-Yin Jhang, Hui-Lin Wang, Yu-Ping Wang
  • Publication number: 20230240151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu- Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20230238043
    Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 11706996
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Si-Han Tsai, Che-Wei Chang, Jing-Yin Jhang
  • Publication number: 20230216337
    Abstract: A stacked power supply system applied for an electronic device is provided. The stacked power supply system has an adapter and multiple battery modules. The adapter has a power plug, a power supply connector and a battery connector. The adapter is connected to an external AC power via the power plug, and converts the alternating current to the direct current, so as to supply power to the electronic device via the power supply connector. The battery modules have a battery set, a first connector and a second connector. The first connector of one of the battery modules is electrically connected to the battery connector of the adapter, the second connector of other neighboring battery modules is adapted to the first connectors of the neighboring battery modules, so as to form a stacked battery modules structure.
    Type: Application
    Filed: May 17, 2022
    Publication date: July 6, 2023
    Inventors: CHIEHWE KU, CHIALIN CHANG, YU-PING WENG
  • Publication number: 20230207637
    Abstract: A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: YU-PING CHEN, CHUN-SHUN HUANG
  • Publication number: 20230200256
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20230200257
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Application
    Filed: February 15, 2023
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20230175077
    Abstract: Provided is a diagnostic system for identifying target microorganisms and/or resistance genes in a sample, including a cell lysis unit, a target nucleic acid enriching unit, a sequencing unit, and a sequence analyzing unit, wherein the cell lysis unit is configured to lyse non-target cells in the sample, the target nucleic acid enriching unit equipped with an immobilized adsorption device is configured to deplete nucleic acids of the non-target cells and to enrich nucleic acids of the target microorganisms, and the sequencing unit and the sequence analyzing unit are configured to produce identification results of the microbial species and/or resistance genes from the sequences of the enriched nucleic acids. Also provided is a method for enriching target nucleic acids in a sample and a method for identifying target microorganisms and/or resistance genes by sequencing the enriched nucleic acids of the target microorganisms.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 8, 2023
    Applicant: CENTERS FOR DISEASE CONTROL, MINISTRY OF HEALTH AND WELFARE
    Inventors: Chien-Shun CHIOU, Hui-Yung SONG, Bo-Han CHEN, Yu-Ping HONG, Min-Chi LU, Hui-Ling TANG
  • Patent number: 11665978
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, Rai-Min Huang, I-Fan Chang, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 11665973
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20230151684
    Abstract: A window blind includes a headrail, two lift cords, a blind body, a bottom rail and two cord winding devices. The two cord winding devices are respectively installed on the bottom of the bottom rail. Subject to the technical feature that the other ends of the two lift cords are respectively tied to the adjustment columns of the two cord winding devices, if the winding stroke is inconsistent and the blind body is folded unevenly or skewed when the window blind is folded or stretched, the adjustment column of one cord winding device can be fine-adjusted to let the respective lift cord be gradually wound and covered on the adjustment column, so that the bottom rail and the blind body can be gradually adjusted to be substantially parallel to the bottom of the headrail, thereby effectively achieving the effect of fine-tuning and correcting the blind body.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 18, 2023
    Applicant: CHING FENG HOME FASHIONS CO., LTD.
    Inventors: SHENG-YING HSU, MING-CHU CHIANG, YU-PING CHOU
  • Publication number: 20230154514
    Abstract: The invention provides a semiconductor structure, which comprises an MTJ (magnetic tunneling junction) stacked structure arranged on a substrate, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.
    Type: Application
    Filed: December 12, 2021
    Publication date: May 18, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin