Abstract: A light-emitting device includes a first type semiconductor layer, an active layer, a second type semiconductor layer disposed adjacent to the active layer and opposite the first type semiconductor layer, and including a current spreading layer that has a recess, an insulation layer filling the recess and protruding from a surface of the current spreading layer that faces in a direction away from the active layer, and a contact layer disposed on the surface of the current spreading layer which lacks said insulation layer. A sum of a depth of the recess and a thickness of the contact layer is not less than a thickness of the insulation layer. A method for producing the light-emitting device is also disclosed.

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Abstract: A light-emitting epitaxial structure includes an n-type ohmic contact layer, an n-type cladding layer, a light emitting layer, a p-type cladding layer, a p-type GaInP transition layer, a p-type AlxGa(1-x)InP transition unit and a p-type GaP ohmic contact layer that are sequentially disposed in such order, wherein in the p-type AlxGa(1-x)InP transition unit, 0<x?0.7. An infrared light-emitting diode including the aforementioned light-emitting epitaxial structure and a method for manufacturing the light-emitting epitaxial structure are also disclosed.

Abstract: A method of separating an edge portion from a glass substrate includes applying a scoring tool of a scoring apparatus to a glass substrate to cause the scoring tool to score the glass substrate along a score line as the glass substrate moves relative to the scoring apparatus and applying a breaker bar of a breaker apparatus to the glass substrate as the glass substrate moves relative to the breaker bar to separate an edge portion from the glass substrate along the score line.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

Abstract: The present disclosure provides systems, apparatus, methods, and computer-readable media that support multi-frame depth-of-field (MF-DOF) for deblurring background regions of interest (ROIs), such as background faces, that may be blurred due to a large aperture size or other characteristics of the camera used to capture the image frame. The processing may include the use of two image frames obtained at two different focus points corresponding to the multiple ROIs in the image frame. The corrected image frame may be determined by deblurring one or more ROIs of the first image frame using an AI-based model and/or local gradient information. The MF-DOF may allow selectively increasing a depth-of-field (DOF) of an image to provide focused capture of multiple regions of interest, without causing a reduction in aperture (and subsequently an amount of light available for photography) or background blur that may be desired for photography.

Abstract: Systems and techniques are provided for processing image data. According to some aspects, a process can include obtaining a frame captured using an image sensor of a device. The process can include detecting an orientation of the device using a position sensor. The process can further include determining, based on the orientation, a transform to be applied to a region of interest in the frame. The process can include applying the transform to the region of interest. The process can further include providing the transformed region of interest to the object detection algorithm.

Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

Abstract: A power backup circuit provides a plurality of input power sources to back up a load. The power backup circuit includes a first switch, a second switch, and a control unit. The input power sources at least includes a first input power source and a second input power source. If the input power source of the load needs to be changed from the first input power source to the second input power source, the control unit controls the first switch to be coupled to the second input power source and controls the second switch to be coupled to the second input power source after the control unit effects a supply current flowing through a first power supply path and a second power supply path both coupled to the first input power source and the load to be reduced below a current threshold.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.