Abstract: Disclosed is a memory device including plural bit lines, plural word lines and a control circuit. The bit lines are configured to receive pixel data of an image. Each word line includes plural factor units. The factor units of each word line are configured differently according to plural factors of a filter. When processing a first area of the image by the filter, the control circuit inputs the pixel data within the first area of the image to the bit lines, and enables one of the word lines for operation. When processing a second area of the image by the filter, the control circuit maintains the pixel data within the second area overlapping the first area on the bit lines, and inputs the pixel data within the second area which doesn't overlap the first area to the bit lines, and enables another one of the word lines for operation.

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Abstract: A module, system and method adjusts a tunable filter to have an adjustable frequency response based on one of an outbound optical signal on a transmit channel and an inbound optical signal on a receive channel. The tunable filter is in an optical path of the outbound optical signal and in an optical path of the inbound optical signal. The transmit and the receive channels are configured as part of a channel plan of a bidirectional (bi-di) dense wavelength division multiplexing (DWDM) system.

Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Abstract: A neuromorphic computing device includes a plurality of row lines, a plurality of column lines and a plurality of synapses. The synapses are positioned at intersections of the row lines and column lines, respectively. The synapses include a first synapse and a second synapse. The first synapse includes a first resistance-adjustable element and a first transistor connected to the first resistance-adjustable element in series. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synapse includes a second resistance-adjustable element and a second transistor connected to the second resistance-adjustable element in series. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio differs from the second aspect ratio, and/or the first turn-on voltage differs from the second turn-on voltage.

Abstract: In an example, a communication module includes an optical transmitter, an optical receiver, and a periodical filter. The optical transmitter is configured to emit an outbound optical signal. The optical receiver is configured to receive an inbound optical signal. A first frequency of the outbound optical signal is offset from a second frequency of the inbound optical signal by an amount less than a channel spacing of a multiplexer/demultiplexer implemented in an optical communication system that includes the communication module. The periodical filter is positioned in optical paths of both the outbound optical signal and the inbound optical signal and has a transmission spectrum with periodic transmission peaks and troughs. The first frequency of the outbound optical signal may be aligned to one of the transmission peaks and the second frequency of the inbound optical signal may be aligned to one of the transmission troughs, or vice versa.

Abstract: A flexible printed circuit board including an annular main board and a plurality of branches connected with the annular main board is provided. Each of the branches includes an extension portion connected with the annular main board and a bonding portion, and an electronic component is adapted to be disposed on the bonding portion. A supporting holder including an annular base, two wing structures, and a plurality of mounting portions is also disclosed, wherein the wing structures extend outward from the annular base and the mounting portions are located on the annular base and the wing structures. Further, a controller including the flexible printed circuit board and the supporting holder aforementioned is disclosed, wherein the annular main board is disposed on the annular base and the branches are disposed on the annular base and the wing structures, such that the bonding portions are located on the mounting portions correspondingly.

Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.

Abstract: An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.

Abstract: An optoelectronic module may include an optical receiver optically coupled with an optical fiber. The optical receiver may be configured to receive time synchronization signals from the optical fiber. The time synchronization signals may be frequency modulated, wavelength modulated, or amplitude modulated and may be received along with received data signals. A time synchronization signal detection module may be communicatively coupled to the optical receiver. The time synchronization signal detection module may be configured to receive the time synchronization signals that are transmitted through the optical fiber and detect frequency modulations, wavelength modulations, or amplitude modulations to recover the time synchronization signals.

Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

Abstract: A system or a network may include an optoelectronic module that includes an optical transmitter optically coupled with an optical fiber, and a controller communicatively coupled to the optical transmitter. The controller may be configured to operate the optical transmitter to transmit data signals through the optical fiber. The optoelectronic module may be configured to transmit time synchronization signals through the optical fiber along with the data signals.

Abstract: A curved display panel includes a first substrate, a second substrate, a display medium located between the first substrate and the second substrate, scan lines, data lines, pixel structures, color filter patterns, shielding patterns, and filling structures. Each pixel structure is electrically connected to one of the scan lines and one of the data lines, and includes an active device and a pixel electrode. The color filter patterns are disposed corresponding to the pixel structures. The shielding patterns are disposed parallel to the data lines, gaps are provided between the shielding patterns and the scan lines, and the shielding patterns are disposed corresponding to junctions of two adjacent color filter patterns. The filling structures are disposed corresponding to the gaps.

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.

Abstract: A ReRAM device is provided. The ReRAM device comprises a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer, and a ReRAM unit disposed on the first conductive connecting structure. The first dielectric layer comprises a first insulating layer disposed on the substrate, and a stop layer disposed on the first insulating layer and contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer.

Abstract: A method for physically unclonable function-identification (PUF-ID) generation includes: providing a PUF array having programmable resistance memory cells; performing a forming procedure followed by a programming procedure on all of the programmable resistance memory cells of the PUF array; performing an estimation process to estimate randomness of the PUF array, by comparing a reference current of a base unit to a total current passing through all of the programmable resistance memory cells for obtaining a PUF randomness; determining a setting result of randomness based on the estimation process; and generating a PUF-ID according to the setting result of randomness.

Abstract: A module, system and method adjusts a tunable filter to have an adjustable frequency response based on one of an outbound optical signal on a transmit channel and an inbound optical signal on a receive channel. The tunable filter is in an optical path of the outbound optical signal and in an optical path of the inbound optical signal. The transmit and the receive channels are configured as part of a channel plan of a bidirectional (bi-di) dense wavelength division multiplexing (DWDM) system.

Abstract: A switch assembly is adapted to be disposed in a holding portion of a hand-held device. The switch assembly includes first and second keys, first and second connecting portions, a switch element and a plunger. The first and second keys are exposed on the surface of the holding portion and respectively disposed on the opposite sides thereof. The first and second connecting portions respectively connect the first and second keys and the holding portion. The first and second connecting portions are disposed for allowing the first key having a displacement toward the second key along their connecting direction. The switch element is located inside of the holding portion, and the first key has a first backside toward the second key. The second key has a second backside toward the first key. The plunger is adapted to press and activate the switch element through the displacement.