Patents by Inventor Yu-Yu Lin

Yu-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10191340
    Abstract: A curved display panel includes a first substrate, a second substrate, a display medium located between the first substrate and the second substrate, scan lines, data lines, pixel structures, color filter patterns, shielding patterns, and filling structures. Each pixel structure is electrically connected to one of the scan lines and one of the data lines, and includes an active device and a pixel electrode. The color filter patterns are disposed corresponding to the pixel structures. The shielding patterns are disposed parallel to the data lines, gaps are provided between the shielding patterns and the scan lines, and the shielding patterns are disposed corresponding to junctions of two adjacent color filter patterns. The filling structures are disposed corresponding to the gaps.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 29, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Sheng-Hsuan Tseng, Chih-Hsien Chi, Ying-Ju Huang, Mei-Hui Lee, Sheng-Shuo Huang, Hung-Che Lin, Sheng-Ju Ho, Yu-Yu Lin
  • Patent number: 10141507
    Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 27, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 10115769
    Abstract: A ReRAM device is provided. The ReRAM device comprises a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer, and a ReRAM unit disposed on the first conductive connecting structure. The first dielectric layer comprises a first insulating layer disposed on the substrate, and a stop layer disposed on the first insulating layer and contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 30, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Feng-Min Lee, Yu-Yu Lin, Kai-Chieh Hsu
  • Patent number: 10103895
    Abstract: A method for physically unclonable function-identification (PUF-ID) generation includes: providing a PUF array having programmable resistance memory cells; performing a forming procedure followed by a programming procedure on all of the programmable resistance memory cells of the PUF array; performing an estimation process to estimate randomness of the PUF array, by comparing a reference current of a base unit to a total current passing through all of the programmable resistance memory cells for obtaining a PUF randomness; determining a setting result of randomness based on the estimation process; and generating a PUF-ID according to the setting result of randomness.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 16, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Yu-Yu Lin, Kai-Chieh Hsu, Feng-Min Lee
  • Publication number: 20180234198
    Abstract: A module, system and method adjusts a tunable filter to have an adjustable frequency response based on one of an outbound optical signal on a transmit channel and an inbound optical signal on a receive channel. The tunable filter is in an optical path of the outbound optical signal and in an optical path of the inbound optical signal. The transmit and the receive channels are configured as part of a channel plan of a bidirectional (bi-di) dense wavelength division multiplexing (DWDM) system.
    Type: Application
    Filed: February 15, 2017
    Publication date: August 16, 2018
    Inventors: Leo Yu-Yu LIN, Huiping LI, Youbin ZHENG, Huade SHU, Li ZHANG
  • Patent number: 10008344
    Abstract: A switch assembly is adapted to be disposed in a holding portion of a hand-held device. The switch assembly includes first and second keys, first and second connecting portions, a switch element and a plunger. The first and second keys are exposed on the surface of the holding portion and respectively disposed on the opposite sides thereof. The first and second connecting portions respectively connect the first and second keys and the holding portion. The first and second connecting portions are disposed for allowing the first key having a displacement toward the second key along their connecting direction. The switch element is located inside of the holding portion, and the first key has a first backside toward the second key. The second key has a second backside toward the first key. The plunger is adapted to press and activate the switch element through the displacement.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: June 26, 2018
    Assignee: HTC Corporation
    Inventors: Yu-Yu Lin, Hung-Chi Shui, Jen-Tsung Chang
  • Patent number: 9959928
    Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 1, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kai-Chieh Hsu, Feng-Min Lee, Yu-Yu Lin
  • Patent number: 9947398
    Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 17, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Kai-Chieh Hsu, Yu-Yu Lin, Feng-Min Lee
  • Patent number: 9947403
    Abstract: A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process includes steps as follows: A programming pulse having a first polarity is firstly applied to at least one resistance switching memory cell of the NVM device. A first verifying pulse with a verifying voltage is then applied to the resistance switching memory cell. A first settling pulse is applied to the resistance switching memory cell prior to or after the verifying pulse is applied, wherein the first settling pulse includes a settling voltage having a second polarity opposite to the first polarity and an absolute value substantially less than that of the verifying voltage.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 17, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Kai-Chieh Hsu
  • Publication number: 20180062825
    Abstract: A system or a network may include an optoelectronic module that includes an optical transmitter optically coupled with an optical fiber, and a controller communicatively coupled to the optical transmitter. The controller may be configured to operate the optical transmitter to transmit data signals through the optical fiber. The optoelectronic module may be configured to transmit time synchronization signals through the optical fiber along with the data signals.
    Type: Application
    Filed: August 30, 2017
    Publication date: March 1, 2018
    Inventors: Puhui Miao, Huade Shu, Leo Yu-yu Lin
  • Patent number: 9871198
    Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: January 16, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Patent number: 9852791
    Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 26, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Ming-Hsiu Lee, Kai-Chieh Hsu, Yu-Yu Lin, Feng-Min Lee
  • Patent number: 9811689
    Abstract: A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 7, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Po-Hao Tseng, Kai-Chieh Hsu, Feng-Min Lee, Yu-Yu Lin
  • Publication number: 20170277007
    Abstract: A curved display panel includes a first substrate, a second substrate, a display medium located between the first substrate and the second substrate, scan lines, data lines, pixel structures, color filter patterns, shielding patterns, and filling structures. Each pixel structure is electrically connected to one of the scan lines and one of the data lines, and includes an active device and a pixel electrode. The color filter patterns are disposed corresponding to the pixel structures. The shielding patterns are disposed parallel to the data lines, gaps are provided between the shielding patterns and the scan lines, and the shielding patterns are disposed corresponding to junctions of two adjacent color filter patterns. The filling structures are disposed corresponding to the gaps.
    Type: Application
    Filed: February 14, 2017
    Publication date: September 28, 2017
    Inventors: Sheng-Hsuan TSENG, Chih-Hsien CHI, Ying-Ju HUANG, Mei-Hui LEE, Sheng-Shuo HUANG, Hung-Che LIN, Sheng-Ju HO, Yu-Yu LIN
  • Publication number: 20170279554
    Abstract: In an example, a communication module includes an optical transmitter, an optical receiver, and a periodical filter. The optical transmitter is configured to emit an outbound optical signal. The optical receiver is configured to receive an inbound optical signal. A first frequency of the outbound optical signal is offset from a second frequency of the inbound optical signal by an amount less than a channel spacing of a multiplexer/demultiplexer implemented in an optical communication system that includes the communication module. The periodical filter is positioned in optical paths of both the outbound optical signal and the inbound optical signal and has a transmission spectrum with periodic transmission peaks and troughs. The first frequency of the outbound optical signal may be aligned to one of the transmission peaks and the second frequency of the inbound optical signal may be aligned to one of the transmission troughs, or vice versa.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 28, 2017
    Inventors: Leo Yu-Yu LIN, Huade SHU, Huiping LI, Li ZHANG, Shanshan ZENG, Guangsheng LI
  • Publication number: 20170188462
    Abstract: A flexible printed circuit board including an annular main board and a plurality of branches connected with the annular main board is provided. Each of the branches includes an extension portion connected with the annular main board and a bonding portion, and an electronic component is adapted to be disposed on the bonding portion. A supporting holder including an annular base, two wing structures, and a plurality of mounting portions is also disclosed, wherein the wing structures extend outward from the annular base and the mounting portions are located on the annular base and the wing structures. Further, a controller including the flexible printed circuit board and the supporting holder aforementioned is disclosed, wherein the annular main board is disposed on the annular base and the branches are disposed on the annular base and the wing structures, such that the bonding portions are located on the mounting portions correspondingly.
    Type: Application
    Filed: March 22, 2016
    Publication date: June 29, 2017
    Inventors: Hung-Chi Shui, Ping-Kun Fu, Min-Jung Hsieh, Yu-Yu Lin, Jen-Tsung Chang, Chih-Lin Chang
  • Patent number: 9691478
    Abstract: A memory architecture has improved controllability of operations for bipolar current directions used to write data in programmable resistance memory cells, including ReRAM cells based on metal oxide memory materials. Instead of a fixed gate voltage on a specific decoder transistor or cell selection device, and a control voltage set to values that cause the decoder transistor or cell selection device to operate in a fully-on mode for one current direction or in a current moderating mode with opposite current direction. Using this technology allows symmetrical or close to symmetrical operation in both current directions with little or no effect on the array complexity.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 27, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee
  • Publication number: 20170179384
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Feng-Min Lee, Yu-Yu Lin
  • Patent number: 9666797
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 30, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Yu-Yu Lin
  • Publication number: 20170133175
    Abstract: A switch assembly is adapted to be disposed in a holding portion of a hand-held device. The switch assembly includes first and second keys, first and second connecting portions, a switch element and a plunger. The first and second keys are exposed on the surface of the holding portion and respectively disposed on the opposite sides thereof. The first and second connecting portions respectively connect the first and second keys and the holding portion. The first and second connecting portions are disposed for allowing the first key having a displacement toward the second key along their connecting direction. The switch element is located inside of the holding portion, and the first key has a first backside toward the second key. The second key has a second backside toward the first key. The plunger is adapted to press and activate the switch element through the displacement.
    Type: Application
    Filed: November 11, 2015
    Publication date: May 11, 2017
    Inventors: Yu-Yu Lin, Hung-Chi Shui, Jen-Tsung Chang