Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.

Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.

Abstract: A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process includes steps as follows: A programming pulse having a first polarity is firstly applied to at least one resistance switching memory cell of the NVM device. A first verifying pulse with a verifying voltage is then applied to the resistance switching memory cell. A first settling pulse is applied to the resistance switching memory cell prior to or after the verifying pulse is applied, wherein the first settling pulse includes a settling voltage having a second polarity opposite to the first polarity and an absolute value substantially less than that of the verifying voltage.

Abstract: A system or a network may include an optoelectronic module that includes an optical transmitter optically coupled with an optical fiber, and a controller communicatively coupled to the optical transmitter. The controller may be configured to operate the optical transmitter to transmit data signals through the optical fiber. The optoelectronic module may be configured to transmit time synchronization signals through the optical fiber along with the data signals.

Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.

Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.

Abstract: A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.

Abstract: A curved display panel includes a first substrate, a second substrate, a display medium located between the first substrate and the second substrate, scan lines, data lines, pixel structures, color filter patterns, shielding patterns, and filling structures. Each pixel structure is electrically connected to one of the scan lines and one of the data lines, and includes an active device and a pixel electrode. The color filter patterns are disposed corresponding to the pixel structures. The shielding patterns are disposed parallel to the data lines, gaps are provided between the shielding patterns and the scan lines, and the shielding patterns are disposed corresponding to junctions of two adjacent color filter patterns. The filling structures are disposed corresponding to the gaps.

Abstract: In an example, a communication module includes an optical transmitter, an optical receiver, and a periodical filter. The optical transmitter is configured to emit an outbound optical signal. The optical receiver is configured to receive an inbound optical signal. A first frequency of the outbound optical signal is offset from a second frequency of the inbound optical signal by an amount less than a channel spacing of a multiplexer/demultiplexer implemented in an optical communication system that includes the communication module. The periodical filter is positioned in optical paths of both the outbound optical signal and the inbound optical signal and has a transmission spectrum with periodic transmission peaks and troughs. The first frequency of the outbound optical signal may be aligned to one of the transmission peaks and the second frequency of the inbound optical signal may be aligned to one of the transmission troughs, or vice versa.

Abstract: A flexible printed circuit board including an annular main board and a plurality of branches connected with the annular main board is provided. Each of the branches includes an extension portion connected with the annular main board and a bonding portion, and an electronic component is adapted to be disposed on the bonding portion. A supporting holder including an annular base, two wing structures, and a plurality of mounting portions is also disclosed, wherein the wing structures extend outward from the annular base and the mounting portions are located on the annular base and the wing structures. Further, a controller including the flexible printed circuit board and the supporting holder aforementioned is disclosed, wherein the annular main board is disposed on the annular base and the branches are disposed on the annular base and the wing structures, such that the bonding portions are located on the mounting portions correspondingly.

Abstract: A memory architecture has improved controllability of operations for bipolar current directions used to write data in programmable resistance memory cells, including ReRAM cells based on metal oxide memory materials. Instead of a fixed gate voltage on a specific decoder transistor or cell selection device, and a control voltage set to values that cause the decoder transistor or cell selection device to operate in a fully-on mode for one current direction or in a current moderating mode with opposite current direction. Using this technology allows symmetrical or close to symmetrical operation in both current directions with little or no effect on the array complexity.

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.

Abstract: A switch assembly is adapted to be disposed in a holding portion of a hand-held device. The switch assembly includes first and second keys, first and second connecting portions, a switch element and a plunger. The first and second keys are exposed on the surface of the holding portion and respectively disposed on the opposite sides thereof. The first and second connecting portions respectively connect the first and second keys and the holding portion. The first and second connecting portions are disposed for allowing the first key having a displacement toward the second key along their connecting direction. The switch element is located inside of the holding portion, and the first key has a first backside toward the second key. The second key has a second backside toward the first key. The plunger is adapted to press and activate the switch element through the displacement.

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.

Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.

Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.

Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.

Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.