Abstract: One embodiment of the disclosure provides a kit for detecting a mutation and/or polymorphism of a specific region in a target nucleotide sequence, including: at least one first primer consisting of a first segment and a second segment, wherein the first segment is a complementary strand of a first sequence and the second segment is a second sequence, and the 3? end of the first segment connects to the 5? end of the second segment; a second primer being a third sequence; at least one third primer consisting of a third segment and a fourth segment, wherein the third segment is a fourth sequence and the fourth segment is a complementary strand of a fifth sequence, and the 3? end of the third segment connects to the 5? end of the fourth segment; and a fourth primer being a complementary strand of a sixth sequence, wherein the specific region includes rs1799853, rs1057910, rs2108622, rs9923231 and rs9934438.

Abstract: A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

Abstract: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.

Abstract: A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

Abstract: Disclosed is a controlling method for fixing a scale ratio of browsing images of a touch device. The controlling method comprises the steps of: determining a zooming region on a display screen, which is determined by pinching the browsing image from a selected position to thus zoom in or zoom out the browsing image, and the scale ratio of zooming is accordingly determined; displaying a screen-locking icon on the display screen, wherein the scale ratio is locked when the screen-locking icon is triggered to be in a locking state; and displaying the other browsing images with the same scale ratio of zooming and with a viewing size same as the zooming region.

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.

Abstract: The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Abstract: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract: A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract: One embodiment of the disclosure provides a kit for detecting a mutation and/or polymorphism of a specific region in a target nucleotide sequence, including: at least one first primer consisting of a first segment and a second segment, wherein the first segment is a complementary strand of a first sequence and the second segment is a second sequence, and the 3? end of the first segment connects to the 5? end of the second segment; a second primer being a third sequence; at least one third primer consisting of a third segment and a fourth segment, wherein the third segment is a fourth sequence and the fourth segment is a complementary strand of a fifth sequence, and the 3? end of the third segment connects to the 5? end of the fourth segment; and a fourth primer being a complementary strand of a sixth sequence, wherein the specific region includes rs1799853, rs1057910, rs2108622, rs9923231 and rs9934438.

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract: Disclosed is a controlling method for fixing a scale ratio of browsing images of a touch device. The controlling method comprises the steps of: determining a zooming region on a display screen, which is determined by pinching the browsing image from a selected position to thus zoom in or zoom out the browsing image, and the scale ratio of zooming is accordingly determined; displaying a screen-locking icon on the display screen, wherein the scale ratio is locked when the screen-locking icon is triggered to be in a locking state; and displaying the other browsing images with the same scale ratio of zooming and with a viewing size same as the zooming region.

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.

Abstract: The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.