Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: An optimizing method and a computing apparatus for a deep learning network and a computer-readable storage medium are provided. In the method, a value distribution is obtained from a pre-trained model. One or more breaking points in a range of the value distribution are determined. Quantization is performed on a part of values of a parameter type in a first section among multiple sections using a first quantization parameter and the other part of values of the parameter type in a second section among the sections using a second quantization parameter. The value distribution is a statistical distribution of values of the parameter type in the deep learning network. The range is divided into the sections by one or more breaking points. The first quantization parameter is different from the second quantization parameter. Accordingly, accuracy drop can be reduced.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: A display may include illumination optics, a ferroelectric liquid crystal on silicon (fLCOS) panel, and a waveguide. The illumination optics may include a red, green, and blue light sources. The fLCOS panel may produce image light by modulating a series of image frames onto illumination light. Control circuitry may control the illumination optics to produce the illumination light for each image frame in the series of image frames according to a green-heavy illumination sequence that includes first, second, and third time periods. The green light source may be active during each of the first, second, and third time periods. This may allow the green light source to be driven with a lower current density than the other light sources without significantly reducing image quality at an eye box. The lower current density may match the peak efficiency of the green light source, thereby minimizing power consumption by the display.

Abstract: Floating fastener includes base including main body provided with through hole, resisting ring protruded inside through hole, seat body extended around main body and docking portion protruded from seat body, positioning member having shank inserted into through hole, head located at one end of shank outside main body, joint portion located at an opposite end of shank to move in and out of docking portion and stopper provided between joint portion and shank to abut against resisting ring, elastic member set on shank and stopped between head and resisting ring, and pad provided with inner hole which is inserted outside docking portion of base, so that pad abuts against seat body near the docking portion. The pad is made of soft material, which can achieve the purpose of absorbing the shaking and vibration of the floating fastener under the influence of external force.

Abstract: A one-piece formed metal heat dissipation plate includes a substrate and multiple heat dissipation strips arranged in a longitudinal direction. The substrate includes a first surface and a second surface arranged opposite to each other. Each of the heat dissipation strips includes two connection ends connected to the first surface, at least two ridge portions arranged between the two connection ends, and multiple concave-convex tooth portions formed on at least one side of at least one of the ridge portions. A cut slot is defined in the substrate corresponding to the at least two ridge portions of each heat dissipation strip, and the cut slot penetrates the first surface and the second surface.

Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A display may have display layers that form an array of pixels. An angle-of-view adjustment layer may overlap the display layers. The angle-of-view adjustment layer may include an array of adjustable light blocking structures formed from electrochromic material. The electrochromic material may be interposed between first and second electrode layers. When it is desired to operate the display in a private viewing mode, control circuitry may apply a current to the first and second electrodes that causes the electrochromic material to become more opaque, thereby restricting the angle of view of the display. When it is desired to operate the display in a public viewing mode, control circuitry may apply a current to the first and second electrodes that causes the electrochromic material to become more transparent, thereby opening up the angle of view of the display.

Abstract: A foldable display device having a foldable display region includes a flexible substrate, a plurality of first light emitting units disposed on the flexible substrate in the foldable display region, and a first protector disposed on at least one of the first light emitting units. The first protector has a surface, and at least a portion of the surface has a curved profile.

Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

Abstract: An electronic device includes a substrate, an electronic element, a transistor, a redistribution layer and a plurality of first bonding pads. The electronic element is disposed on the substrate. The transistor is electrically connected with the electronic element. The plurality of first bonding pads are disposed on the redistribution layer.

Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.

Abstract: A display device is provided and includes at least two sub-pixels. One of the sub-pixels is a blue sub-pixel. Each of the sub-pixels includes a light emitting unit and a light converting layer disposed on the light emitting unit. A thickness of the light converting layer of another one of the sub-pixels is greater than a thickness of the light converting layer of the one of the sub-pixels. The one of the sub-pixels emits an output light under an operation of the highest gray level, the output light is a final visual light of the blue sub-pixel of the display device, and the output light has an output spectrum. A wavelength of a first wave of the output spectrum ranges from 380 nm to 493 nm, and a full width at half maximum of the first wave ranges from 10 nm to 30 nm.