Abstract: An electronic device includes a substrate, a plurality of connecting pads, a plurality of conductive portions overlapped with the plurality of connecting pads, a plurality of conductive lines, an insulating layer, and an integrated chip. At least one of the conductive lines is overlapped with at least one of the conductive portions, and at least one of the connecting pads is electrically connected to the at least one of the conductive lines through the at least one of the conductive portions. The insulating layer is disposed between the at least one of the connecting pads and the at least one of the conductive portions, wherein the insulating layer directly contacts a top surface and a lateral surface of the at least one of the conductive portions. The integrated chip is electrically connected to the at least one of the conductive lines.

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.

Abstract: A device and systems for cooling hardware components is disclosed. The smart cold plate (CP) device includes a first inlet port for supplying a first coolant path, a second inlet port for supplying a second coolant path, and a valve for selectively controlling a flow of a coolant between the first and second inlet ports and an internal port, the internal port connecting the first and second inlet ports to a CP. The device also includes an external port connected to the CP for removing the coolant from the smart CP device and a connector through which power is supplied to the valve. Various cooling systems incorporating the smart CP device are disclosed.

Abstract: A color aligning method of display for a computer system having a processing unit, a display and a server includes determining, by the server, a color information file of the display according to a related information of the display; downloading, by the processing unit, the color information file of the display from the server; and enabling, by the processing unit, the color information file according to a preset mode of the display.

Abstract: A new pharmaceutical use of potassium ATP channel modulator, namely potassium ATP channel modulator (such as diazoxide, cromakalim, pinacidil, nicorandil, and aprikalim, etc.) in preparation of antidiabetic nephropathy drugs, is provided. Also provided with a potassium ATP channel modulator as an active ingredient of the pharmaceutical composition is used for the prevention or treatment of diabetic nephropathy. A diabetic rat model created by streptozotocin (STZ) is used and a diabetic nephropathy model with a high-fat diet in rats is generated. Urine microalbumin (mALB) is used as an indicator to test whether the rat enters diabetic nephropathy. In addition, rat body weight and its blood glucose level are used as an indicator to decide whether the model is successful. The experimental results showed that the administration of potassium ATP channel openers such as diazoxide to diabetic rats could delay the process of kidney injury in diabetic rats.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: An anti-reflective coating composition comprises an organic polymer. The organic polymer comprises a crosslinkable polymer. The crosslinkable polymer comprises a monomer unit formed by a monomer represented by formula (I): wherein R1 is selected from substituted or unsubstituted C2-C10 alkenyl, and R2 and R3 are each independently selected from H, substituted or unsubstituted C1-C6 alkyl, and substituted or unsubstituted C6-C20 aryl. Compared with the prior art, the subject crosslinkable polymer comprises the monomer unit that can be self-crosslinked with functional groups such as hydroxyl, amino, and sulfhydryl, such that a crosslinking agent does not need to be added to a coating. The generation of gas during baking process of the composition can be effectively reduced or eliminated, and some unnecessary cleaning process is avoided by doing so. The pattern damage due to solid particle caused by gas condensation can also be avoided.

Abstract: In one embodiment, an apparatus comprises a processor to: receive a request to configure a secure execution environment for a first workload; configure a first set of secure execution enclaves for execution of the first workload, wherein the first set of secure execution enclaves is configured on a first set of processing resources, wherein the first set of processing resources comprises one or more central processing units and one or more accelerators; configure a first set of secure datapaths for communication among the first set of secure execution enclaves during execution of the first workload, wherein the first set of secure datapaths is configured over a first set of interconnect resources; configure the secure execution environment for the first workload, wherein the secure execution environment comprises the first set of secure execution enclaves and the first set of secure datapaths.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.

Abstract: A method includes forming a fin over a semiconductor layer, depositing an isolation feature on sidewalls of the fin, recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer, forming a sacrificial feature in the first trench, forming an epitaxial feature over the sacrificial feature, exposing a bottom surface of the sacrificial feature, removing the sacrificial feature to form a second trench exposing a bottom surface of the epitaxial feature, and forming a conductive feature in the second trench. The conductive feature electrically couples to the epitaxial feature.

Abstract: Semiconductor structures and processes are provided. A semiconductor structure according to the present disclosure includes a channel region of a semiconductor body rising above an isolation feature, a gate structure wrapping over the channel region, a source/drain feature in contact with a sidewall of the channel region, a backside silicide layer disposed on a bottom surface of the source/drain feature, and a backside contact feature extending through the isolation feature to contact a bottom surface of the backside silicide layer. A sidewall of the backside contact feature is spaced apart from the isolation feature by a first backside contact etch stop layer (CESL) and a second backside CESL.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: An electronic device is provided by the present disclosure. The electronic device includes a substrate and at least one electronic unit. The substrate has at least one recess, and the at least one electronic unit is disposed in the at least one recess. The at least one electronic unit has N1 signal connecting points, wherein N1 is greater than or equal to 1. In a top view direction of the electronic device, the at least one recess has a maximum size D1, the at least one electronic unit has a maximum size C1, and the maximum size D1 and the maximum size C1 satisfies: 0<D1?C1<C1/N1.

Abstract: An impact powered torque wrench has a force-applying rod. The force-applying rod is connected to a transmission rod. A transmission shaft is disposed in the transmission rod. Two ends of the transmission shaft are connected to a head unit and a drive unit, respectively. A trip unit and an adjustment unit are provided between the force-applying rod and the transmission rod. An impact unit is provided between the transmission shaft and the drive unit. The drive unit drives the transmission shaft by means of intermittent impact, which increases the output torque and has a higher level of operational safety.

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas.

Abstract: A mask includes a reflective layer, an absorption layer and an absorption part. The absorption layer is disposed over the reflective multilayer. The absorption part is disposed in the reflective layer and the absorption layer, wherein an entire top surface of the absorption part is substantially flush with a top surface of the absorption layer.