Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: An electronic device and a manufacturing thereof are disclosed. The electronic device includes a first conductive layer, a first insulating layer, a second insulating layer, a second conductive layer, a plurality of semiconductor elements and a covering layer. The first insulating layer is disposed on the first conductive layer. In a cross-sectional view of the electronic device, the first insulating layer has two side-surfaces which are opposite to each other. The second insulating layer is disposed on the first insulating layer and in contact with the two side-surfaces of the first insulating layer. The second conductive layer is disposed on the second insulating layer and electrically connected to the first conductive layer. The plurality of semiconductor elements are disposed on the second conductive layer and electrically connected to the second conductive layer. The covering layer is disposed on the plurality of semiconductor elements.

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Abstract: A wind turbine planet gear shaft has a shaft body with an outer surface, a segment of the outer surface being a slide bearing surface configured to form a radial slide bearing with an inner opening of a planet gear. The slide bearing surface has a first portion configured as a non-load-bearing zone and a second portion configured as a load-bearing zone and exactly one axially elongate oil pocket in the slide bearing surface, that oil pocket being located in the non-load-bearing zone. An oil supply channel in the shaft body has a first end in communication with the oil pocket, and first and second oil return channels in the slide bearing surface each have a first end at a longitudinal end of the oil pocket and a second end open to ambient air.

Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: An adjustable garden sprinkler has a base member and a plurality of irrigators. The base member has a first main body and a second main body, a plurality of connecting pipes protruding from the second main body, and a plurality of connecting pipes are provided on one side of the periphery of the connecting pipes. Each irrigator has a first housing and a second housing that opposite to each other, and a control member is provided between the first and the second housings. The control member is provided with a plurality of first through aperture, a plurality of second through aperture and a plurality of third through aperture, one end of the control member is provided with an outer threaded pipe extending out of the first housing and the second housing, a screwing cap is attached on the outer threaded pipe, and a spraying unit installed inside the first housing.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: The present disclosure relates to an elastic fiber, an elastic fiber covered yarn and reeling manufacturing methods thereof. The reeling manufacturing method of an elastic fiber includes: providing an elastic fiber material, the elastic fiber material having a core portion and a skin portion, the skin portion covering the core portion; performing a first extending, to have the elastic fiber material passing a first guiding roller, the speed of the first guiding roller being 500-1500 m/min; performing a second extending, to have the elastic fiber material passing a second guiding roller, the speed of the second guiding roller being 1200-2400 m/min; and performing a third extending, to have the elastic fiber material passing a third guiding roller, the speed of the third guiding roller is 1300-2600 m/min.

Abstract: A mask includes a reflective layer, an absorption layer, a buffer layer and an absorption part. The absorption layer is disposed over the reflective layer. The buffer layer is disposed between the reflective layer and the absorption layer. The absorption part is disposed in the reflective layer, the buffer layer and the absorption layer.

Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process.

Abstract: A method for manufacturing a hydrocarbon compound from carbon dioxide, said method including: (a) a step of preparing an absorption-conversion catalyst that includes an oxide carrier, a first component supported on the oxide carrier and including at least one type of metal selected from the group consisting of alkali metals and alkaline earth metals, and a second component supported on the oxide carrier and including at least one type of metal selected from the group consisting of Ni, Fe, Co, Cu, and Ru; (b) a step of bringing the absorption-conversion catalyst and a carbon dioxide-including gas into contact under higher pressure than atmospheric pressure, and causing the carbon dioxide to be stored in the absorption-conversion catalyst; and (c) a step of bringing the absorption-conversion catalyst that has the carbon dioxide stored therein and a reducing gas into contact under higher pressure than atmospheric pressure, and obtaining the hydrocarbon compound.

Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.