Abstract: A quantum dot includes a nanocrystalline core and a nanocrystalline shell. The nanocrystalline core includes a core body and a doping material that is non-uniformly doped in the core body. The core body has a sphalerite-type crystal structure, and includes at least one element from Group IB, at least one element from Group IIIA and at least one element from Group VIA. The doping material includes at least one doping element selected from the group consisting of an element from Group IB, an element from Group IIB and an element from Group IIIA. The nanocrystalline shell surrounds the nanocrystalline core and includes at least one element from Group VIA, and at least one element from one of Group IIB and Group IIIA. A method for preparing the quantum dot is also disclosed.

Abstract: A cell-nanoparticle drug delivery system includes mesenchymal stem cells and gadolinium-based agent-loaded magnetic nanoparticles which are internalized into the mesenchymal stem cells. Each of the gadolinium-based agent-loaded magnetic nanoparticles includes a core that is loaded with gadolinium-based agent and that includes a fucoidan-based inner core layer with the fucoidan non-covalently bound to the gadolinium-based agent, and a shell which includes superparamagnetic iron oxide-based inner shell layer with the superparamagnetic iron oxide bound to the gadolinium-based agent through electrical attraction, and an outer shell layer made of fucoidan and polyvinyl alcohol. Methods for inhibiting the growth of tumor cells and diagnosing the tumor cells in a subject using the cell-nanoparticle drug delivery system are also provided.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a nanostructure, an isolation structure, an isolation fin, and a gate stack. The method includes turning the substrate upside down and removing the base to expose the isolation structure. The method includes partially removing the isolation structure to form a first trench in the isolation structure. The first trench exposes a portion of the isolation fin. The method includes removing the portion of the isolation fin through the first trench to form a second trench in the gate stack. The method includes partially removing the gate stack through the first trench and the second trench. The second trench passes through the gate stack and divides the gate stack into a first part and a second part.

Abstract: A plasticizer, a plastic composition and a plastic product are provided. The plasticizer composition and the plastic product include the plasticizer, and the plasticizer has a biodegradability. The plasticizer has a structure represented by Formula (I), in which each of the symbols thereof is as defined in the specification, and the plasticizer has a central structure.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.

Abstract: A gardening sprinkler may include a main body, a sprinkler member, and a control base, and the main body has a sprinkler base and an upper cover which are adapted to fit together. The sprinkler base is a hollow tube and has an opening at one end thereof, the sprinkler member is positioned into the sprinkler base through the opening, and a water inlet member is connected to the sprinkler base through the opening. The sprinkler base has a concaved portion and a sprinkler surface, and the concaved portion is formed adjacent to the other end of the opening. The sprinkler surface comprises a row of first through holes which are arranged axially, and upper cover has a row of second through holes at positions corresponding to the first through holes.

Abstract: A display device includes a first display unit and a second display unit. The first display unit emits a red light having a first output spectrum corresponding to a highest gray level of the display device. The second display unit emits a blue light having a second output spectrum corresponding to the highest gray level of the display device. An intensity integral of the first output spectrum within a range from 380 nm to 780 nm is defined as a first intensity integral, an intensity integral of the second output spectrum within a range from 511 nm to 597 nm is defined as a second intensity integral, and a ratio of the second intensity integral to the first intensity integral is greater than 0% and less than or equal to 29.0%.

Abstract: A cooling system for a heat-generating electronic device includes a cold plate module, a flow channel, and a fin arrangement. The cold plate module includes a base plate and a top cover. The flow channel is for a liquid coolant and extends between an inlet connector and an outlet connector. The liquid coolant flows along a flow direction. The fin arrangement is located between the base plate and the top cover. The fin arrangement is thermally coupled to the flow channel and is eccentrically located relative to the cold plate module.

Abstract: A system may have windows. A window in the system may have first and second window layers such as structural layers of glass. The window may have a light guide layer between the first and second window layers. The light guide layer may have cladding layers and a core layer between the cladding layers. The core and cladding refractive index values may be selected so that the refractive index of the core is greater than the refractive index of the structural layers of glass while the refractive index of the claddings is less than the refractive index of the structural layer of glass. Light-scattering structures may be formed on the light guide to extract some of the light within the light guide and thereby provide illumination for the system.

Abstract: A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.

Abstract: In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

Abstract: The present disclosure provides a nanocapsule comprising a hydrophilic core; and a hydrophobic shell enclosing the hydrophilic core. The hydrophobic shell contains an outer layer comprising fucoidan, a middle layer comprising carotenoids and metal oxide nanoparticles, and an inner layer comprising fucoidan and contacting the hydrophilic core. The present disclosure also provides use of the nanocapsule as disclosed herein in the manufacture of a medicament for treating and/or diagnosing diseases in a subject in need thereof.

Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.